Datasheet

XIO2001
www.ti.com SCPS212G –MAY 2009–REVISED DECEMBER 2012
4.67 Clock Mask Register
This register selects which PCI bus clocks are disabled when bits 22:20 (POWER_OVRD) in the general
control register (offset D4h, see Section 4.65) are set to 010h or 011h. This register has no effect on the
clock outputs if the POWER_OVRD bits are not set to 010h or 011h or if the slot power limit is greater
than the power required. See Table 4-41 for a complete description of the register contents.
PCI register offset: D9h
Register type: Read-only, Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
Table 4-41. Clock Mask Register Description
BIT FIELD NAME ACCESS DESCRIPTION
7 RSVD R Reserved. Returns 0b when read.
6
(1)
Clock output 6 mask. This bit disables CLKOUT6 when the POWER_OVRD bits are set to
010b or 011b and the slot power limit is exceeded.
CLOCK6_MASK RW
0 = Clock enabled (default)
1 = Clock disabled
5
(1)
Clock output 5 mask. This bit disables CLKOUT5 when the POWER_OVRD bits are set to
010b or 011b and the slot power limit is exceeded.
CLOCK5_MASK RW
0 = Clock enabled (default)
1 = Clock disabled
4
(1)
Clock output 4 mask. This bit disables CLKOUT4 when the POWER_OVRD bits are set to
010b or 011b and the slot power limit is exceeded.
CLOCK4_MASK RW
0 = Clock enabled (default)
1 = Clock disabled
3
(1)
Clock output 3 mask. This bit disables CLKOUT3 when the POWER_OVRD bits are set to
010b or 011b and the slot power limit is exceeded.
CLOCK3_MASK RW
0 = Clock enabled (default)
1 = Clock disabled
2
(1)
Clock output 2 mask. This bit disables CLKOUT2 when the POWER_OVRD bits are set to
010b or 011b and the slot power limit is exceeded.
CLOCK2_MASK RW
0 = Clock enabled (default)
1 = Clock disabled
1
(1)
Clock output 1 mask. This bit disables CLKOUT1 when the POWER_OVRD bits are set to
010b or 011b and the slot power limit is exceeded.
CLOCK1_MASK RW
0 = Clock enabled (default)
1 = Clock disabled
0
(1)
Clock output 0 mask. This bit disables CLKOUT0 when the POWER_OVRD bits are set to
010b or 011b and the slot power limit is exceeded.
CLOCK0_MASK RW
0 = Clock enabled (default)
1 = Clock disabled
(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Copyright © 2009–2012, Texas Instruments Incorporated Classic PCI Configuration Space 79
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