Datasheet

XIO2001
www.ti.com SCPS212G –MAY 2009–REVISED DECEMBER 2012
Table 4-39. General Control Register Description (continued)
BIT FIELD NAME ACCESS DESCRIPTION
22:20
(1)
POWER_OVRD RW Power override. This bit field determines how the bridge responds when the slot power limit is
less than the amount of power required by the bridge and the devices behind the bridge.
000 = Ignore slot power limit (default).
001 = Assert the PWR_OVRD terminal.
010 = Disable secondary clocks selected by the clock mask register.
011 = Disable secondary clocks selected by the clock mask register and assert the
PWR_OVRD terminal.
100 = Respond with unsupported request to all transactions except for configuration
transactions (type 0 or type 1) and set slot power limit messages.
101,110, Reserved
111 =
19
(1)
READ_PREFETC RW Read Prefetch Disable. This bit is used to control the pre-fetch functionality on PCI memory read
H_DIS transactions.
0 = Memory read, memory read line, and memory read multiple will be treated as
prefetchable reads (default)
1 = Memory read line, and memory read multiple will be treated as pre-fetchable reads.
Memory read will not be prefetchable. No auto-prefetch reads will be made for these
requests.
18:16
(1)
L0s_LATENCY RW L0s maximum exit latency. This field programs the maximum acceptable latency when exiting the
L0s state. This sets bits 8:6 (EP_L0S_LAT) in the device capabilities register (offset 74h, see
Section 4.49).
000 = Less than 64 ns (default)
001 = 64 ns up to less than 128 ns
010 = 128 ns up to less than 256 ns
011 = 256 ns up to less than 512 ns
100 = 512 ns up to less than 1 μs
101 = 1 μs up to less than 2 μs
110 = 2 μs to 4 μs
111 = More than 4 μs
15:13
(2)
L1_LATENCY RW L1 maximum exit latency. This field programs the maximum acceptable latency when exiting the
L1 state. This sets bits 11:9 (EP_L1_LAT) in the device capabilities register (offset 74h, see
Section 4.49).
000 = Less than 1 μs (default)
001 = 1 μs up to less than 2 μs
010 = 2 μs up to less than 4 μs
011 = 4 μs up to less than 8 μs
100 = 8 μs up to less than 16 μs
101 = 6 μs up to less than 32 μs
110 = 32 μs to 64 μs
111 = More than 64 μs
12
(2)
VC_CAP_EN R VC Capability Structure Enable. This bit is hardwired to 0b indicating that the VC Capability
structure is permanently disabled.
11
(3)
BPCC_E RW Bus power clock control enable. This bit controls whether the secondary bus PCI clocks are
stopped when the XIO2001 is placed in the D3 state. It is assumed that if the secondary bus
clocks are required to be active, that a reference clock continues to be provided on the PCI
Express interface.
0 = Secondary bus clocks are not stopped in D3 (default)
1 = Secondary bus clocks are stopped on D3
10
(3)
BEACON_ENABL RW Beacon enable. This bit controls the mechanism for waking up the physical PCI Express link
E when in L2.
0 = WAKE mechanism is used exclusively. Beacon is not used (default)
1 = Beacon and WAKE mechanisms are used
(2) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
(3) These bits are sticky and must retain their value when the bridge is powered by V
AUX
.
Copyright © 2009–2012, Texas Instruments Incorporated Classic PCI Configuration Space 77
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