Datasheet

XIO2001
SCPS212G –MAY 2009–REVISED DECEMBER 2012 www.ti.com
4.65 General Control Register
This read/write register controls various functions of the bridge. See Table 4-39 for a complete description
of the register contents.
PCI register offset: D4h
Register type: Read-only, Read/Write
Default value: 8600 025Fh
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 1 0 0 1 0 1 1 1 1 1
Table 4-39. General Control Register Description
BIT FIELD NAME ACCESS DESCRIPTION
31:30
(1)
CFG_RETRY_CN RW Configuration retry counter. Configures the amount of time that a configuration request must be
TR retried on the secondary PCI bus before it may be completed with configuration retry status on
the PCI Express side.
00 = 25 μs
01 = 1 ms
10 = 25 ms (default)
11 = 50 ms
29:28
(1)
ASPM_CTRL_DE RW Active State Power Management Control Default Override. These bits are used to determine the
F_OVRD power up default for bits 1:0 of the Link Control Register in the PCI Express Capability Structure.
00 = Power on default indicates that the active state power management is disable (00b)
01 = (default)
10 = Power on default indicates that the active state power management is enabled for L0s
11 = (01b)
Power on default indicates that the active state power management is enabled for L1s
(10b)
Power on default indicates that the active state power management is enabled for L0s
and L1s (11b)
27
(1)
LOW_POWER_E RW Low-power enable. When this bit is set, the half-amplitude, no pre-emphasis mode for the PCI
N Express TX drivers is enabled. The default for this bit is 0b.
26
(1)
PCI_PM_VERSIO RW PCI power management version control. This bit controls the value reported in bits 2:0
N_CTRL (PM_VERSION) in the power management capabilities register (offset 4Ah, see Section 4.36). It
also controls the value of bit 3 (NO_SOFT_RESET) in the power management control/status
register (offset 4Ch, see Section 4.37).
0 = Version fields reports 010b and NO_SOFT_RESET reports 0b for Power
Management 1.1 compliance
1 = Version fields reports 011b and NO_SOFT_RESET reports 1b for Power
Management 1.2 compliance (default)
25
(1)
RSVD RW Reserved. Bit 25 defaults to 0b. If this register is programmed via EEPROM or another
mechanism, then the value written into this field must be 0b.
24 RSVD R Reserved. Returns 0b when read.
23
(1)
CPM_EN_DEF_O RW Clock power management enable default override. This bit determines the power-up default for
VRD bits 1:0 (CPM_EN) of the link control register (offset 80h, see Section 4.53) in the PCI Express
Capability structure.
0 = Power-on default indicates that clock power management is disabled (00b) (default)
1 = Power-on default indicates that clock power management is enabled for L0s and L1
(11b)
(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
76 Classic PCI Configuration Space Copyright © 2009–2012, Texas Instruments Incorporated
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