Datasheet

XIO2001
www.ti.com SCPS212G –MAY 2009–REVISED DECEMBER 2012
Table 4-35. Control and Diagnostic Register 0 Description (continued)
ACCES
BIT FIELD NAME S DESCRIPTION
18 ALT_ERROR_REP RW Alternate Error Reporting. This bit controls the method that the XIO2001 uses for error
reporting.
0 = Advisory Non-Fatal Error reporting supported (default)
1 = Advisory Non-Fatal Error reporting not supported
17:16 RSVD R Reserved. Returns 00b when read.
15:14
(1)
RSVD RW Reserved. Bits 15:14 default to 00b. If this register is programmed via EEPROM or another
mechanism, the value written into this field must be 00b.
13:12 RSVD R Reserved. Returns 00b when read.
11:7
(1)
RSVD RW Reserved. Bits 11:7 default to 00000b. If this register is programmed via EEPROM or
another mechanism, the value written into this field must be 00000b.
6:3 RSVD R Reserved. Returns 0h when read.
2
(1)
CFG_ACCESS RW Configuration access to memory-mapped registers. When this bit is set, the bridge allows
_MEM_REG configuration access to memory-mapped configuration registers.
1
(1)
RSVD RW Reserved. Bit 1 defaults to 0b. If this register is programmed via EEPROM or another
mechanism, the value written into this field must be 0b.
0
(1)
FORCE_CLKREQ RW Force CLKREQ. When this bit is set, the bridge will force the CLKREQ output to always be
asserted. The default setting for this bit is 1b.
4.62 Control and Diagnostic Register 1
The contents of this register are used for monitoring status and controlling behavior of the bridge. See
Table 4-36 for a complete description of the register contents. It is recommended that all values within this
register be left at the default value. Improperly programming fields in this register may cause
interoperability or other problems.
PCI register offset: C4h
Register type: Read/Write
Default value: 0012 0108h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0
Table 4-36. Control and Diagnostic Register 1 Description
BIT FIELD NAME ACCESS DESCRIPTION
32:21 RSVD R Reserved. Returns 000h when read.
20:18
(1)
L1_EXIT_LAT_A RW L1 exit latency for asynchronous clock. When bit 6 (CCC) of the link control register (offset
SYNC 80h, see Section 4.53) is set, the value in this field is mirrored in bits 17:15 (L1_LATENCY)
field in the link capabilities register (offset 7Ch, see Section 4.52). This field defaults to 100b.
17:15
(1)
L1_EXIT_LAT_C RW L1 exit latency for common clock. When bit 6 (CCC) of the link control register (offset 80h, see
OMMON Section 4.53) is clear, the value in this field is mirrored in bits 17:15 (L1_LATENCY) field in the
link capabilities register (offset 7Ch, see Section 4.52). This field defaults to 100b.
14:11
(1)
RSVD RW Reserved. Bits 14:11 default to 0000b. If this register is programmed via EEPROM or another
mechanism, the value written into this field must be 0000b.
10
(1)
SBUS_RESET_M RW Secondary bus reset bit mask. When this bit is set, the bridge masks the reset caused by bit 6
ASK (SRST) of the bridge control register (offset 3Eh, see Section 4.29). This bit defaults to 0b.
9:6
(1)
L1ASPM_TIMER RW L1ASPM entry timer. This field specifies the value (in 512-ns ticks) of the L1ASPM entry timer.
This field defaults to 0100b.
5:2
(1)
L0s_TIMER RW L0s entry timer. This field specifies the value (in 62.5-MHz clock ticks) of the L0s entry timer.
This field defaults to 0010b.
(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Copyright © 2009–2012, Texas Instruments Incorporated Classic PCI Configuration Space 73
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