Datasheet
XIO2001
SCPS212G –MAY 2009–REVISED DECEMBER 2012
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4.60 GPIO Data Register
This register reads the state of the input mode GPIO terminals and changes the state of the output mode
GPIO terminals. Writing to a bit that is in input mode or is enabled for a secondary function is ignored. The
secondary functions share GPIO0 (CLKRUN), GPIO1 (PWR_OVRD), GPIO3 (SDA), and GPIO4 (SCL).
The default value at power up depends on the state of the GPIO terminals as they default to general-
purpose inputs. See Table 4-34 for a complete description of the register contents.
PCI register offset: B6h
Register type: Read-only, Read/Write
Default value: 00XXh
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 x x x x x
Table 4-34. GPIO Data Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:5 RSVD R Reserved. Returns 000h when read.
4
(1)
GPIO4_DATA RW GPIO 4 data. This bit reads the state of GPIO4 when in input mode or changes the state of
GPIO4 when in output mode.
3
(1)
GPIO3_DATA RW GPIO 3 data. This bit reads the state of GPIO3 when in input mode or changes the state of
GPIO3 when in output mode.
2
(1)
GPIO2_DATA RW GPIO 2 data. This bit reads the state of GPIO2 when in input mode or changes the state of
GPIO2 when in output mode.
1
(1)
GPIO1_DATA RW GPIO 1 data. This bit reads the state of GPIO1 when in input mode or changes the state of
GPIO1 when in output mode.
0
(1)
GPIO0_DATA RW GPIO 0 data. This bit reads the state of GPIO0 when in input mode or changes the state of
GPIO0 when in output mode.
(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
4.61 TL Control and Diagnostic Register 0
The contents of this register are used for monitoring status and controlling behavior of the bridge. See
Table 4-35 for a complete description of the register contents. It is recommended that all values within this
register be left at the default value. Improperly programming fields in this register may cause
interoperability or other problems.
PCI register offset: C0h
Register type: Read/Write
Default value: 0000 0001h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Table 4-35. Control and Diagnostic Register 0 Description
ACCES
BIT FIELD NAME S DESCRIPTION
31:24
(1)
PRI_BUS_NUM R This field contains the captured primary bus number.
23:19
(1)
PRI_DEVICE_ NUM R This field contains the captured primary device number.
(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
72 Classic PCI Configuration Space Copyright © 2009–2012, Texas Instruments Incorporated
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