Datasheet

XIO2001
SCPS212G –MAY 2009–REVISED DECEMBER 2012 www.ti.com
Table 4-29. Link Control Register Description (continued)
BIT FIELD NAME ACCESS DESCRIPTION
8 CPM_EN RW Clock Power Management Enable. This bit is used to enable the bridge to use CLKREQ
for clock power management
0 = Clock Power Management is disabled. CLKREQ is held low.
1 = Clock Power Management is enabled and the bridge is permitted to use the
CLKREQ signal to allow the REFCLK input to be stopped
The default value for this is bit is determined by bit 23 (CPM_EN_DEF_OVRD) in
the general control register (offset D4h, see Section 4.65).
7 ES RW Extended synch. This bit forces the bridge to extend the transmission of FTS ordered sets
and an extra TS2 when exiting from L1 prior to entering to L0.
0 = Normal synch (default)
1 = Extended synch
6 CCC RW Common clock configuration. When this bit is set, it indicates that the bridge and the
device at the opposite end of the link are operating with a common clock source. A value
of 0b indicates that the bridge and the device at the opposite end of the link are operating
with separate reference clock sources. The bridge uses this common clock configuration
information to report the L0s and L1 exit latencies.
0 = Reference clock is asynchronous (default)
1 = Reference clock is common
5 RL R Retrain link. This bit has no function and is read-only 0b.
4 LD R Link disable. This bit has no function and is read-only 0b.
3 RCB RW Read completion boundary. This bit is an indication of the RCB of the root complex. The
state of this bit has no affect on the bridge, since the RCB of the bridge is fixed at 128
bytes.
0 = 64 bytes (default)
1 = 128 bytes
2 RSVD R Reserved. Returns 0b when read.
1:0 ASLPMC RW Active state link PM control. This field enables and disables the active state PM. The
default value for this is bit is determined by bits 29:28 (ASPM_CTRL_DEF_OVRD) in the
general control register (offset D4h, see Section 4.65).
00 = Active state PM disabled (default)
01 = L0s entry enabled
10 = L1 entry enabled
11 = L0s and L1 entry enabled
4.54 Link Status Register
The link status register indicates the current state of the PCI Express link. See Table 4-30 for a complete
description of the register contents.
PCI register offset: 82h
Register type: Read-only
Default value: X011h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 x 0 0 0 0 0 0 0 1 0 0 0 1
Table 4-30. Link Status Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15 LABW R Link autonomous bandwidth status. This bit has no function and is read-only 0b.
14 LBWM R Link bandwidth management status. This bit has no function and is read-only 0b.
13 DLLLA R Data link layer link active. This bit has no function and is read-only 0b.
68 Classic PCI Configuration Space Copyright © 2009–2012, Texas Instruments Incorporated
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