Datasheet

XIO2001
www.ti.com SCPS212G –MAY 2009–REVISED DECEMBER 2012
Table 4-28. Link Capabilities Register Description
BIT FIELD NAME ACCESS DESCRIPTION
31:24 PORT_NUM R Port number. This field indicates port number for the PCI Express link. This field is read-only
00h indicating that the link is associated with port 0.
23:22 RSVD R Reserved. Return 00b when read.
21 LBN_CAP R Link bandwidth notification. This bit is hardwired to 0b since this field is not applicable to a
bridge.
20 DLLLAR_CAP R DLL link active reporting capable. This bit is hardwired to 0b since the bridge does not support
this capability.
19 SDER_CAP R Surprise down error reporting capable. This bit is hardwired to 0b since the bridge does not
support this capability.
18 CLK_PM R Clock Power Management. This bit is hardwired to 1 to indicate that XIO2001 supports Clock
Power Management through CLKREQ protocol.
17:15 L1_LATENCY R L1 exit latency. This field indicates the time that it takes to transition from the L1 state to the L0
state. Bit 6 (CCC) in the link control register (offset 80h, see Section 4.53) equals 1b for a
common clock and equals 0b for an asynchronous clock.
For a common reference clock, the value of this field is determined by bits 20:18
(L1_EXIT_LAT_ASYNC) of the control and diagnostic register 1 (offset C4h, see Section 4.62).
For an asynchronous reference clock, the value of this field is determined by bits 17:15
(L1_EXIT_LAT_COMMON) of the control and diagnostic register 1 (offset C4h, see
Section 4.62).
14:12 L0S_LATENCY R L0s exit latency. This field indicates the time that it takes to transition from the L0s state to the
L0 state. Bit 6 (CCC) in the link control register (offset 80h, see Section 4.53) equals 1b for a
common clock and equals 0b for an asynchronous clock.
For a common reference clock, the value of 011b indicates that the L1 exit latency falls between
256 ns to less than 512 ns.
For an asynchronous reference clock, the value of 100b indicates that the L1 exit latency falls
between 512 ns to less than 1 μs.
11:10 ASLPMS R Active state link PM support. This field indicates the level of active state power management
that the bridge supports. The value 11b indicates support for both L0s and L1 through active
state power management.
9:4 MLW R Maximum link width. This field is encoded 00 0001b to indicate that the bridge only supports a
x1 PCI Express link.
3:0 MLS R Maximum link speed. This field is encoded 1h to indicate that the bridge supports a maximum
link speed of 2.5 Gb/s.
4.53 Link Control Register
The link control register controls link specific behavior. See Table 4-29 for a complete description of the
register contents.
PCI register offset: 80h
Register type: Read-only, Read/Write
Default value: 0Y0Xh
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 y 0 0 0 0 0 0 x x
Table 4-29. Link Control Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:12 RSVD R Reserved. Returns 0h when read.
11 LABW_IEN R Link autonomous bandwidth interrupt enable. This bit is hardwired to 0b since this field is
not applicable to a bridge.
10 LBWN_IEN R Link bandwidth management interrupt enable. This bit is hardwired to 0b since this field is
not applicable to a bridge.
9 HWAW_DIS R Hardware autonomous width disable. This bit is hardwired to 0b since this field is not
supported by this bridge.
Copyright © 2009–2012, Texas Instruments Incorporated Classic PCI Configuration Space 67
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