Datasheet

XIO2001
www.ti.com SCPS212G –MAY 2009–REVISED DECEMBER 2012
4.50 Device Control Register
The device control register controls PCI Express device specific parameters. See Table 4-26 for a
complete description of the register contents.
PCI register offset: 78h
Register type: Read-only, Read/Write
Default value: 2000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4-26. Device Control Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15 CFG_RTRY_ENB RW Configuration retry status enable. When this read/write bit is set to 1b, the bridge returns a
completion with completion retry status on PCI Express if a configuration transaction
forwarded to the secondary interface did not complete within the implementation specific time-
out period. When this bit is set to 0b, the bridge does not generate completions with
completion retry status on behalf of configuration transactions. The default value of this bit is
0b.
14:12 MRRS RW Maximum read request size. This field is programmed by host software to set the maximum
size of a read request that the bridge can generate. The bridge uses this field to determine
how much data to fetch on a read request. This field is encoded as:
000 = 128B
001 = 256B
010 = 512B (default)
011 = 1024B
100 = 2048B
101 = 4096B
110 = Reserved
111 = Reserved
11 ENS R Enable no snoop. This bit is hardwired to 0 since this device never sets the No Snoop attribute
in transactions that it initiates.
10 APPE RW Auxiliary power PM enable. This bit has no effect in the bridge.
0 = AUX power is disabled (default)
1 = AUX power is enabled
9 PFE R Phantom function enable. Since the bridge does not support phantom functions, this bit is
read-only 0b.
8 ETFE R Extended tag field enable. Since the bridge does not support extended tags, this bit is read-
only 0b.
7:5 MPS RW Maximum payload size. This field is programmed by host software to set the maximum size of
posted writes or read completions that the bridge can initiate. This field is encoded as:
000 = 128B (default)
001 = 256B
010 = 512B
011 = 1024B
100 = 2048B
101 = 4096B
110 = Reserved
111 = Reserved
4 ERO R Enable relaxed ordering. Since the bridge does not support relaxed ordering, this bit is read-
only 0b.
3 URRE RW Unsupported request reporting enable. If this bit is set, then the bridge sends an
ERR_NONFATAL message to the root complex when an unsupported request is received.
0 = Do not report unsupported requests to the root complex (default)
1 = Report unsupported requests to the root complex
2 FERE RW Fatal error reporting enable. If this bit is set, then the bridge is enabled to send ERR_FATAL
messages to the root complex when a system error event occurs.
0 = Do not report fatal errors to the root complex (default)
1 = Report fatal errors to the root complex
Copyright © 2009–2012, Texas Instruments Incorporated Classic PCI Configuration Space 65
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