Datasheet

XIO2001

www.ti.com

SCPS212G –MAY 2009–REVISED DECEMBER 2012

4.46 PCI Express Capability ID Register

This read-only register identifies the linked list item as the register for subsystem ID and subsystem

vendor ID capabilities. The register returns 10h when read.

PCI register offset: 70h

Default value: 10h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 1 0 0 0 0

4.47 Next Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge.

This register reads 00h, indicating no additional capabilities are supported.

PCI register offset: 71h

Default value: 00h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0

4.48 PCI Express Capabilities Register

This read-only register indicates the capabilities of the bridge related to PCI Express. See Table 4-24 for a

complete description of the register contents.

PCI register offset: 72h

Default value: 0072h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1

Table 4-24. PCI Express Capabilities Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15:14 RSVD R Reserved. Returns 00b when read.

13:9 INT_NUM R Interrupt message number. This field is used for MSI support and is implemented as read-

only 00000b in the bridge.

8 SLOT R Slot implemented. This bit is not valid for the bridge and is read-only 0b.

7:4 DEV_TYPE R Device/port type. This read-only field returns 0111b indicating that the device is a PCI

Express-to-PCI bridge.

3:0 VERSION R Capability version. This field returns 2h indicating revision 2 of the PCI Express capability.

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