Datasheet

XIO2001
www.ti.com SCPS212G –MAY 2009–REVISED DECEMBER 2012
Table 4-18. Power Management Capabilities Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:11 PME_SUPPORT R PME support. This 5-bit field indicates the power states from which the bridge may assert
PME. Because the bridge never generates a PME except on a behalf of a secondary
device, this field is read-only and returns 00000b.
10 D2_SUPPORT R This bit returns a 1b when read, indicating that the function supports the D2 device power
state.
9 D1_SUPPORT R This bit returns a 1b when read, indicating that the function supports the D1 device power
state.
8:6 AUX_CURRENT R 3.3 V
AUX
auxiliary current requirements. This field returns 000b since the bridge does not
generate PME from D3
cold
.
5 DSI R Device specific initialization. This bit returns 0b when read, indicating that the bridge does
not require special initialization beyond the standard PCI configuration header before a
generic class driver is able to use it.
4 RSVD R Reserved. Returns 0b when read.
3 PME_CLK R PME clock. This bit returns 0b indicating that the PCI clock is not needed to generate PME.
2:0 PM_VERSION R Power management version. If bit 26 (PCI_PM_VERSION_CTRL) in the general control
register (offset D4h, see Section 4.65) is 0b, then this field returns 010b indicating revision
1.1 compatibility. If PCI_PM_VERSION_CTRL is 1b, then this field returns 011b indicating
revision 1.2 compatibility.
4.37 Power Management Control/Status Register
This register determines and changes the current power state of the bridge. No internal reset is generated
when transitioning from the D3
hot
state to the D0 state. See Table 4-19 for a complete description of the
register contents.
PCI register offset: 4Ch
Register type: Read-only, Read/Write
Default value: 0008h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Table 4-19. Power Management Control/Status Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15 PME_STAT R PME status. This bit is read-only and returns 0b when read.
14:13 DATA_SCALE R Data scale. This 2-bit field returns 00b when read since the bridge does not use the data
register.
12:9 DATA_SEL R Data select. This 4-bit field returns 0h when read since the bridge does not use the data
register.
8 PME_EN RW PME enable. This bit has no function and acts as scratchpad space. The default value for
this bit is 0b.
7:4 RSVD R Reserved. Returns 0h when read.
3 NO_SOFT_RESET R No soft reset. If bit 26 (PCI_PM_VERSION_CTRL) in the general control register (offset
D4h, see Section 4.65) is 0b, then this bit returns 0b for compatibility with version 1.1 of the
PCI Power Management Specification. If PCI_PM_VERSION_CTRL is 1b, then this bit
returns 1b indicating that no internal reset is generated and the device retains its
configuration context when transitioning from the D3
hot
state to the D0 state.
2 RSVD R Reserved. Returns 0b when read.
1:0 PWR_STATE RW Power state. This 2-bit field determines the current power state of the function and sets the
function into a new power state. This field is encoded as follows:
00 = D0 (default)
01 = D1
10 = D2
11 = D3
hot
Copyright © 2009–2012, Texas Instruments Incorporated Classic PCI Configuration Space 59
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