Datasheet

XIO2001

SCPS212G –MAY 2009–REVISED DECEMBER 2012

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4.33 Subsystem ID Register

This register, used for system and option card identification purposes, may be required for certain

operating systems. This read-only register is initialized through the EEPROM and can be written through

the subsystem alias register. This register is reset by a PCI Express reset (PERST), a GRST, or the

internally-generated power-on reset.

PCI register offset: 46h

Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

4.34 Capability ID Register

This read-only register identifies the linked list item as the register for PCI Power Management ID

Capabilities. The register returns 01h when read.

PCI register offset: 48h

Default value: 01h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 1

4.35 Next Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge.

This register reads 50h pointing to the MSI Capabilities registers.

PCI register offset: 49h

Default value: 50h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 1 0 1 0 0 0 0

4.36 Power Management Capabilities Register

This read-only register indicates the capabilities of the bridge related to PCI power management. See

Table 4-18 for a complete description of the register contents.

PCI register offset: 4Ah

Default value: 0603h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1

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