Datasheet

XIO2001

www.ti.com

SCPS212G –MAY 2009–REVISED DECEMBER 2012

Table 4-17. Bridge Control Register Description (continued)

BIT FIELD NAME ACCESS DESCRIPTION

0 PERR_EN RW Parity error response enable. Controls the bridge's response to data, uncorrectable

address, and attribute errors on the secondary interface. Also, the bridge always forwards

data with poisoning, from conventional PCI to PCI Express on an uncorrectable

conventional PCI data error, regardless of the setting of this bit.

0 = Ignore uncorrectable address, attribute, and data errors on the secondary interface

(default)

1 = Enable uncorrectable address, attribute, and data error detection and reporting on

the secondary interface

4.30 Capability ID Register

This read-only register identifies the linked list item as the register for Subsystem ID and Subsystem

Vendor ID capabilities. The register returns 0Dh when read.

PCI register offset: 40h

Default value: 0Dh

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 1 1 0 1

4.31 Next Item Pointer Register

The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge.

This register reads 48h pointing to the PCI Power Management Capabilities registers.

PCI register offset: 41h

Default value: 48h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 1 0 0 1 0 0 0

4.32 Subsystem Vendor ID Register

This register, used for system and option card identification purposes, may be required for certain

operating systems. This read-only register is initialized through the EEPROM and can be written through

the subsystem access register at offset D0h. This register is reset by a PCI Express reset (PERST), a

GRST, or the internally-generated power-on reset.

PCI register offset: 44h

Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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