Datasheet

XIO2001
SCPS212G –MAY 2009–REVISED DECEMBER 2012 www.ti.com
Table 4-17. Bridge Control Register Description (continued)
BIT FIELD NAME ACCESS DESCRIPTION
5 MAM RW Master abort mode. This bit controls the behavior of the bridge when it receives a master
abort or an unsupported request.
0 = Do not report master aborts. Returns FFFF FFFFh on reads and discard data on
writes (default)
1 = Respond with an unsupported request on PCI Express when a master abort is
received on PCI. Respond with target abort on PCI when an unsupported request
completion on PCI Express is received. This bit also enables error signaling on
master abort conditions on posted writes.
4 VGA16 RW VGA 16-bit decode. This bit enables the bridge to provide full 16-bit decoding for VGA I/O
addresses. This bit only has meaning if the VGA enable bit is set.
0 = Ignore address bits [15:10] when decoding VGA I/O addresses (default)
1 = Decode address bits [15:10] when decoding VGA I/O addresses
3 VGA RW VGA enable. This bit modifies the response by the bridge to VGA compatible addresses.
If this bit is set, then the bridge decodes and forwards the following accesses on the
primary interface to the secondary interface (and, conversely, block the forwarding of
these addresses from the secondary to primary interface):
• Memory accesses in the range 000A 0000h to 000B FFFFh
• I/O addresses in the first 64 KB of the I/O address space (address bits [31:16] are
0000h) and where address bits [9:0] are in the range of 3B0h to 3BBh or 3C0h to
3DFh (inclusive of ISA address aliases – address bits [15:10] may possess any
value and are not used in the decoding)
If this bit is set, then forwarding of VGA addresses is independent of the value of bit 2
(ISA), the I/O address and memory address ranges defined by the I/O base and limit
registers, the memory base and limit registers, and the prefetchable memory base and
limit registers of the bridge. The forwarding of VGA addresses is qualified by bits 0
(IO_ENB) and 1 (MEMORY_ENB) in the command register (offset 04h, see Section 4.3).
0 = Do not forward VGA compatible memory and I/O addresses from the primary to
secondary interface (addresses defined above) unless they are enabled for
forwarding by the defined I/O and memory address ranges (default).
1 = Forward VGA compatible memory and I/O addresses (addresses defined above)
from the primary interface to the secondary interface (if the I/O enable and memory
enable bits are set) independent of the I/O and memory address ranges and
independent of the ISA enable bit.
2 ISA RW ISA enable. This bit modifies the response by the bridge to ISA I/O addresses. This
applies only to I/O addresses that are enabled by the I/O base and I/O limit registers and
are in the first 64 KB of PCI I/O address space (0000 0000h to 0000 FFFFh). If this bit is
set, then the bridge blocks any forwarding from primary to secondary of I/O transactions
addressing the last 768 bytes in each 1-KB block. In the opposite direction (secondary to
primary), I/O transactions are forwarded if they address the last 768 bytes in each 1K
block.
0 = Forward downstream all I/O addresses in the address range defined by the I/O
base and I/O limit registers (default)
1 = Forward upstream ISA I/O addresses in the address range defined by the I/O base
and I/O limit registers that are in the first 64 KB of PCI I/O address space (top 768
bytes of each 1-KB block)
1 SERR_EN RW SERR enable. This bit controls forwarding of system error events from the secondary
interface to the primary interface. The bridge forwards system error events when:
• This bit is set
• Bit 8 (SERR_ENB) in the command register (offset 04h, see Section 4.3) is set
• SERR is asserted on the secondary interface
0 = Disable the forwarding of system error events (default)
1 = Enable the forwarding of system error events
56 Classic PCI Configuration Space Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: XIO2001