Datasheet

XIO2001

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SCPS212G –MAY 2009–REVISED DECEMBER 2012

4.23 Prefetchable Limit Upper 32-Bit Register

This read/write register specifies the upper 32 bits of the prefetchable memory limit register. See Table 4-

14 for a complete description of the register contents.

PCI register offset: 2Ch

Default value: 0000 0000h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-14. Prefetchable Limit Upper 32-Bit Register Description

BIT FIELD NAME ACCESS DESCRIPTION

Prefetchable memory limit upper 32 bits. Defines the upper 32 bits of the highest address of the

31:0 PRELIMIT RW prefetchable memory address range that determines when to forward memory transactions

downstream.

4.24 I/O Base Upper 16-Bit Register

This read/write register specifies the upper 16 bits of the I/O base register. See Table 4-15 for a complete

description of the register contents.

PCI register offset: 30h

Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4-15. I/O Base Upper 16-Bit Register Description

BIT FIELD NAME ACCESS DESCRIPTION

I/O base upper 16 bits. Defines the upper 16 bits of the lowest address of the I/O address range

15:0 IOBASE RW that determines when to forward I/O transactions downstream. These bits correspond to address

bits [31:20] in the I/O address. The lower 20 bits are assumed to be 00000h.

4.25 I/O Limit Upper 16-Bit Register

This read/write register specifies the upper 16 bits of the I/O limit register. See Table 4-16 for a complete

description of the register contents.

PCI register offset: 32h

Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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