Datasheet

XIO2001
www.ti.com SCPS212G –MAY 2009–REVISED DECEMBER 2012
4.4 Status Register
The status register provides information about the PCI Express interface to the system. See Table 4-3 for
a complete description of the register contents.
PCI register offset: 06h
Register type: Read-only, Read/Clear
Default value: 0010h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
Table 4-3. Status Register Description
BIT FIELD NAME ACCESS DESCRIPTION
Detected parity error. This bit is set when the PCI Express interface receives a poisoned
TLP. This bit is set regardless of the state of bit 6 (PERR_ENB) in the command register
(offset 04h, see Section 4.3).
15 PAR_ERR RCU
0 = No parity error detected
1 = Parity error detected
Signaled system error. This bit is set when the bridge sends an ERR_FATAL or
ERR_NONFATAL message and bit 8 (SERR_ENB) in the command register (offset 04h,
see Section 4.3) is set.
14 SYS_ERR RCU
0 = No error signaled
1 = ERR_FATAL or ERR_NONFATAL signaled
Received master abort. This bit is set when the PCI Express interface of the bridge
receives a completion-with-unsupported-request status.
13 MABORT RCU
0 = Unsupported request not received on the PCI Express interface
1 = Unsupported request received on the PCI Express interface
Received target abort. This bit is set when the PCI Express interface of the bridge receives
a completion-with-completer-abort status.
12 TABORT_REC RCUT
0 = Completer abort not received on the PCI Express interface
1 = Completer abort received on the PCI Express interface
Signaled target abort. This bit is set when the PCI Express interface completes a request
with completer abort status.
11 TABORT_SIG RCUT
0 = Completer abort not signaled on the PCI Express interface
1 = Completer abort signaled on the PCI Express interface
10:9 PCI_SPEED R DEVSEL timing. These bits are read-only 00b, because they do not apply to PCI Express.
Master data parity error. This bit is set if bit 6 (PERR_ENB) in the command register (offset
04h, see Section 4.3) is set and the bridge receives a completion with data marked as
poisoned on the PCI Express interface or poisons a write request received on the PCI
8 DATAPAR RCU
Express interface.
0 = No uncorrectable data error detected on the primary interface
1 = Uncorrectable data error detected on the primary interface
Fast back-to-back capable. This bit does not have a meaningful context for a PCI Express
7 FBB_CAP R
device and is hardwired to 0b.
6 RSVD R Reserved. Returns 0b when read.
66-MHz capable. This bit does not have a meaningful context for a PCI Express device and
5 66MHZ R
is hardwired to 0b.
Capabilities list. This bit returns 1b when read, indicating that the bridge supports additional
4 CAPLIST R
PCI capabilities.
Interrupt status. This bit reflects the interrupt status of the function. This bit is read-only 0b
3 INT_STATUS R
since the bridge does not generate any interrupts internally.
2:0 RSVD R Reserved. Returns 000b when read.
Copyright © 2009–2012, Texas Instruments Incorporated Classic PCI Configuration Space 45
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