Datasheet

XIO2001
SCPS212G –MAY 2009–REVISED DECEMBER 2012 www.ti.com
4.3 Command Register
The command register controls how the bridge behaves on the PCI Express interface. See Table 4-2 for a
complete description of the register contents.
PCI register offset: 04h
Register type: Read-only, Read/Write
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4-2. Command Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:11 RSVD R Reserved. Returns 00000b when read.
INTx disable. This bit enables device specific interrupts. Since the bridge does not
10 INT_DISABLE R
generate any internal interrupts, this bit is read-only 0b.
Fast back-to-back enable. The bridge does not generate fast back-to-back transactions;
9 FBB_ENB R
therefore, this bit returns 0b when read.
SERR enable bit. When this bit is set, the bridge can signal fatal and nonfatal errors on the
PCI Express interface on behalf of SERR assertions detected on the PCI bus.
8 SERR_ENB RW
0 = Disable the reporting of nonfatal errors and fatal errors (default)
1 = Enable the reporting of nonfatal errors and fatal errors
Address/data stepping control. The bridge does not support address/data stepping, and
7 STEP_ENB R
this bit is hardwired to 0b.
Controls the setting of bit 8 (DATAPAR) in the status register (offset 06h, see Section 4.4)
in response to a received poisoned TLP from PCI Express. A received poisoned TLP is
forwarded with bad parity to conventional PCI regardless of the setting of this bit.
6 PERR_ENB RW
0 = Disables the setting of the master data parity error bit (default)
1 = Enables the setting of the master data parity error bit
VGA palette snoop enable. The bridge does not support VGA palette snooping; therefore,
5 VGA_ENB R
this bit returns 0b when read.
Memory write and invalidate enable. When this bit is set, the bridge translates PCI
Express memory write requests into memory write and invalidate transactions on the PCI
interface.
4 MWI_ENB RW
0 = Disable the promotion to memory write and invalidate (default)
1 = Enable the promotion to memory write and invalidate
Special cycle enable. The bridge does not respond to special cycle transactions; therefore,
3 SPECIAL R
this bit returns 0b when read.
Bus master enable. When this bit is set, the bridge is enabled to initiate transactions on
the PCI Express interface.
0 = PCI Express interface cannot initiate transactions. The bridge must disable the
2 MASTER_ENB RW
response to memory and I/O transactions on the PCI interface (default).
1 = PCI Express interface can initiate transactions. The bridge can forward memory
and I/O transactions from PCI secondary interface to the PCI Express interface.
Memory space enable. Setting this bit enables the bridge to respond to memory
transactions on the PCI Express interface.
0 = PCI Express receiver cannot process downstream memory transactions and must
1 MEMORY_ENB RW
respond with an unsupported request (default)
1 = PCI Express receiver can process downstream memory transactions. The bridge
can forward memory transactions to the PCI interface.
I/O space enable. Setting this bit enables the bridge to respond to I/O transactions on the
PCI Express interface.
0 = PCI Express receiver cannot process downstream I/O transactions and must
0 IO_ENB RW
respond with an unsupported request (default)
1 = PCI Express receiver can process downstream I/O transactions. The bridge can
forward I/O transactions to the PCI interface.
44 Classic PCI Configuration Space Copyright © 2009–2012, Texas Instruments Incorporated
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