Datasheet

XIO2001
www.ti.com SCPS212G –MAY 2009–REVISED DECEMBER 2012
Table 4-1. Classic PCI Configuration Register Map (continued)
REGISTER NAME OFFSET
Device Status 2 Device Control 2 098h
Link Capabilities 2 09Ch
Link Status 2 Link Control 2 0A0h
Slot Capabilities 2 0A4h
Slot Status 2 Slot Control 2 0A8h
Reserved 0ACh
Serial-bus control and Serial-bus slave address
(1)
Serial-bus word address
(1)
Serial-bus data
(1)
0B0h
status
(1)
GPIO data
(1)
GPIO control
(1)
0B4h
Reserved 0B8h–0BCh
TL Control and diagnostic register 0
(1)
0C0h
DLL Control and diagnostic register 1
(1)
0C4h
PHY Control and diagnostic register 2
(1)
0C8h
Reserved 0CCh
Subsystem access
(2)
0D0h
General control
(2)
0D4h
Reserved Clock run status
(2)
Clock mask Clock control 0D8h
Reserved Arbiter time-out status Arbiter request mask
(2)
Arbiter control
(2)
0DCh
Serial IRQ edge control
(2)
Reserved Serial IRQ mode control
(2)
0E0h
Reserved Serial IRQ status 0E4h
Cache Timer Transfer Limit PFA Request Limit 0E8h
Cache Timer Upper Limit Cache Timer Lower Limit 0ECh
Reserved 0F0h–0FCh
(2) One or more bits in this register are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Registers highlighted in gray are reserved or not implemented.
4.1 Vendor ID Register
This 16-bit read-only register contains the value 104Ch, which is the vendor ID assigned to Texas
Instruments.
PCI register offset: 00h
Register type: Read-only
Default value: 104Ch
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0
4.2 Device ID Register
This 16-bit read-only register contains the value 8231h, which is the device ID assigned by TI for the
bridge.
PCI register offset: 02h
Register type: Read-only
Default value: 8240h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0
Copyright © 2009–2012, Texas Instruments Incorporated Classic PCI Configuration Space 43
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