Datasheet

XIO2001
SCPS212G –MAY 2009–REVISED DECEMBER 2012 www.ti.com
4.60 GPIO Data Register ....................................................................................................... 72
4.61 TL Control and Diagnostic Register 0 .................................................................................. 72
4.62 Control and Diagnostic Register 1 ...................................................................................... 73
4.63 Control and Diagnostic Register 2 ...................................................................................... 74
4.64 Subsystem Access Register ............................................................................................. 74
4.65 General Control Register ................................................................................................. 76
4.66 Clock Control Register .................................................................................................... 78
4.67 Clock Mask Register ...................................................................................................... 79
4.68 Clock Run Status Register ............................................................................................... 80
4.69 Arbiter Control Register ................................................................................................... 81
4.70 Arbiter Request Mask Register .......................................................................................... 83
4.71 Arbiter Time-Out Status Register ........................................................................................ 84
4.72 Serial IRQ Mode Control Register ...................................................................................... 84
4.73 Serial IRQ Edge Control Register ....................................................................................... 85
4.74 Serial IRQ Status Register ............................................................................................... 87
4.75 Pre-Fetch Agent Request Limits Register .............................................................................. 88
4.76 Cache Timer Transfer Limit Register ................................................................................... 89
4.77 Cache Timer Lower Limit Register ...................................................................................... 90
4.78 Cache Timer Upper Limit Register ...................................................................................... 90
5 PCI Express Extended Configuration Space ......................................................................... 91
5.1 Advanced Error Reporting Capability ID Register ..................................................................... 91
5.2 Next Capability Offset/Capability Version Register ................................................................... 92
5.3 Uncorrectable Error Status Register .................................................................................... 92
5.4 Uncorrectable Error Mask Register ..................................................................................... 93
5.5 Uncorrectable Error Severity Register .................................................................................. 94
5.6 Correctable Error Status Register ....................................................................................... 95
5.7 Correctable Error Mask Register ........................................................................................ 96
5.8 Advanced Error Capabilities and Control Register .................................................................... 97
5.9 Header Log Register ...................................................................................................... 97
5.10 Secondary Uncorrectable Error Status Register ...................................................................... 98
5.11 Secondary Uncorrectable Error Mask Register ....................................................................... 99
5.12 Secondary Uncorrectable Error Severity .............................................................................. 100
5.13 Secondary Error Capabilities and Control Register ................................................................. 101
5.14 Secondary Header Log Register ....................................................................................... 102
6 Memory-Mapped TI Proprietary Register Space ................................................................... 103
6.1 Device Control Map ID Register ....................................................................................... 103
6.2 Revision ID Register ..................................................................................................... 104
6.3 GPIO Control Register .................................................................................................. 104
6.4 GPIO Data Register ..................................................................................................... 105
6.5 Serial-Bus Data Register ................................................................................................ 106
6.6 Serial-Bus Word Address Register .................................................................................... 106
6.7 Serial-Bus Slave Address Register .................................................................................... 106
6.8 Serial-Bus Control and Status Register ............................................................................... 107
6.9 Serial IRQ Mode Control Register ..................................................................................... 108
6.10 Serial IRQ Edge Control Register ..................................................................................... 108
6.11 Serial IRQ Status Register .............................................................................................. 110
6.12 Pre-Fetch Agent Request Limits Register ............................................................................ 112
6.13 Cache Timer Transfer Limit Register .................................................................................. 113
6.14 Cache Timer Lower Limit Register .................................................................................... 113
6.15 Cache Timer Upper Limit Register .................................................................................... 114
7 Electrical Characteristics .................................................................................................. 115
7.1 Absolute Maximum Ratings ............................................................................................ 115
7.2 Recommended Operating Conditions ................................................................................. 115
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