Datasheet

XIO2001
SCPS212G –MAY 2009–REVISED DECEMBER 2012 www.ti.com
Table 3-8. EEPROM Register Loading Map (continued)
SERIAL EEPROM WORD BYTE DESCRIPTION
ADDRESS
07h PCI D5h, general control, byte 1
08h PCI D6h, general control, byte 2
09h PCI D7h, general control, byte 3
0Ah PCI D8h, clock control
0Bh PCI D9h, clock mask
0Ch Reserved—no bits loaded
0Dh PCI DCh, arbiter control
0Eh PCI DDh, arbiter request mask
0Fh PCI C0h, control and diagnostic register, byte 0
10h PCI C1h, control and diagnostic register, byte 1
11h PCI C2h, control and diagnostic register, byte 2
12h PCI C3h, control and diagnostic register, byte 3
13h PCI C4h, control and diagnostic register, byte 0
14h PCI C5h, control and diagnostic register, byte 1
15h PCI C6h, control and diagnostic register, byte 2
15h PCI C6h, control and diagnostic register, byte 2
16h PCI C7h, control and diagnostic register, byte 3
17h PCI C8h, control and diagnostic register, byte 0
18h PCI C9h, control and diagnostic register, byte 1
19h PCI CAh, control and diagnostic register, byte 2
1Ah PCI CBh, control and diagnostic register, byte 3
1Bh Reserved—no bits loaded
1Ch Reserved—no bits loaded
1Dh PCI E0h, serial IRQ mode control
1Eh PCI E2h, serial IRQ edge control, byte 0
1Fh PCI E3h, serial IRQ edge control, byte 1
20h PCI E8h, PFA_REQ_LENGTH_LIMIT
21h PCI E9h, PFA_REQ_CNT_LIMIT
22h PCI EAh, CACHE_TMR_XFR_LIMIT
23h PCI ECh, CACHE_TIMER_LOWER_LIMIT, Byte 0
24h PCI EDh, CACHE_TIMER_LOWER_LIMIT, Byte 1
25h PCI EEh, CACHE_TIMER_UPPER_LIMIT, Byte 0
26h PCI EFh, CACHE_TIMER_UPPER_LIMIT, Byte 1
27h End-of-list indicator (80h)
This format must be explicitly followed for the bridge to correctly load initialization values from a serial
EEPROM. All byte locations must be considered when programming the EEPROM.
The serial EEPROM is addressed by the bridge at slave address 1010 000b. This slave address is
internally hardwired and cannot be changed by the system designer. Therefore, all three hardware
address bits for the EEPROM are tied to V
SS
to achieve this address. The serial EEPROM in the sample
application circuit (Figure 3-13) assumes the 1010b high-address nibble. The lower three address bits are
terminal inputs to the chip, and the sample application shows these terminal inputs tied to V
SS
.
During an EEPROM download operation, bit 4 (ROMBUSY) in the serial-bus control and status register is
asserted. After the download is finished, bit 0 (ROM_ERR) in the serial-bus control and status register
may be monitored to verify a successful download.
38 Feature/Protocol Descriptions Copyright © 2009–2012, Texas Instruments Incorporated
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