Datasheet

XIO2001
www.ti.com SCPS212G –MAY 2009–REVISED DECEMBER 2012
Figure 3-17. Serial-Bus Protocol – Byte Read
Figure 3-18 illustrates the serial interface protocol during a multi-byte serial EEPROM download. The
serial-bus protocol starts exactly the same as a 1-byte read. The only difference is that multiple data bytes
are transferred. The number of transferred data bytes is controlled by the bridge master. After each data
byte, the bridge master issues acknowledge (logic low) if more data bytes are requested. The transfer
ends after a bridge master no acknowledge (logic high) followed by a stop condition.
Figure 3-18. Serial-Bus Protocol – Multibyte Read
Bit 7 (PROT_SEL) in the serial-bus control and status register changes the serial-bus protocol. Each of
the three previous serial-bus protocol figures illustrates the PROT_SEL bit default (logic low). When this
control bit is asserted, the word address and corresponding acknowledge are removed from the serial-bus
protocol. This feature allows the system designer a second serial-bus protocol option when selecting
external EEPROM devices.
3.10.3 Serial-Bus EEPROM Application
The registers and corresponding bits that are loaded through the EEPROM are provided in Table 3-8.
Table 3-8. EEPROM Register Loading Map
SERIAL EEPROM WORD BYTE DESCRIPTION
ADDRESS
00h PCI-Express to PCI bridge function indicator (00h)
01h Number of bytes to download (25h)
02h PCI 44h, subsystem vendor ID, byte 0
03h PCI 45h, subsystem vendor ID, byte 1
04h PCI 46h, subsystem ID, byte 0s
05h PCI 47h, subsystem ID, byte 1s
06h PCI D4h, general control, byte 0
Copyright © 2009–2012, Texas Instruments Incorporated Feature/Protocol Descriptions 37
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