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XIO2001
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SCPS212G –MAY 2009–REVISED DECEMBER 2012
3.10.1 Serial-Bus Interface Implementation
To enable the serial-bus interface, a pullup resistor must be implemented on the SCL signal. At the rising
edge of PERST or GRST, whichever occurs later in time, the SCL terminal is checked for a pullup resistor.
If one is detected, then bit 3 (SBDETECT) in the serial-bus control and status register (see Section 4.58)
is set. Software may disable the serial-bus interface at any time by writing a 0b to the SBDETECT bit. If
no external EEPROM is required, then the serial-bus interface is permanently disabled by attaching a
pulldown resistor to the SCL signal.
The bridge implements a two-terminal serial interface with one clock signal (SCL) and one data signal
(SDA). The SCL signal is a unidirectional output from the bridge and the SDA signal is bidirectional. Both
are open-drain signals and require pullup resistors. The bridge is a bus master device and drives SCL at
approximately 60 kHz during data transfers and places SCL in a high-impedance state (0 frequency)
during bus idle states. The serial EEPROM is a bus slave device and must acknowledge a slave address
equal to A0h. Figure 3-13 illustrates an example application implementing the two-wire serial bus.
Figure 3-13. Serial EEPROM Application
3.10.2 Serial-Bus Interface Protocol
All data transfers are initiated by the serial-bus master. The beginning of a data transfer is indicated by a
start condition, which is signaled when the SDA line transitions to the low state while SCL is in the high
state, as illustrated in Figure 3-14. The end of a requested data transfer is indicated by a stop condition,
which is signaled by a low-to-high transition of SDA while SCL is in the high state, as shown in Figure 3-
14. Data on SDA must remain stable during the high state of the SCL signal, as changes on the SDA
signal during the high state of SCL are interpreted as control signals, that is, a start or stop condition.
Figure 3-14. Serial-Bus Start/Stop Conditions and Bit Transfers
Copyright © 2009–2012, Texas Instruments Incorporated Feature/Protocol Descriptions 35
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