Datasheet

DataAddress
CLK
FRAME
LOCK
AD
IRDY
TRDY
DEVSEL
XIO2001
www.ti.com SCPS212G –MAY 2009–REVISED DECEMBER 2012
Figure 3-9. PCI Express PME Message
3.9 PCI Express to PCI Bus Lock Conversion
The bus-locking protocol defined in the PCI Express Base Specification and PCI Local Bus Specification is
provided on the bridge as an additional compatibility feature. The PCI bus LOCK signal is a dedicated
output that is enabled by setting bit 12 in the general control register at offset D4h. See Section 4.65,
General Control Register, for details.
NOTE
The use of LOCK is only supported by PCI-Express to PCI Bridges in the downstream
direction (away from the root complex).
PCI Express locked-memory read request transactions are treated the same as PCI Express memory read
transactions except that the bridge returns a completion for a locked-memory read. Also, the bridge uses
the PCI LOCK protocol when initiating the memory read transaction on the PCI bus.
When a PCI Express locked-memory read request transaction is received and the bridge is not already
locked, the bridge arbitrates for use of the LOCK terminal by asserting REQ. If the bridge receives GNT
and the LOCK terminal is high, then the bridge drives the LOCK terminal low after the address phase of
the first locked-memory read transaction to take ownership of LOCK. The bridge continues to assert
LOCK except during the address phase of locked transactions. If the bridge receives GNT and the LOCK
terminal is low, then the bridge deasserts its REQ and waits until LOCK is high and the bus is idle before
re-arbitrating for the use of LOCK.
Figure 3-10. Starting a Locked Sequence
Copyright © 2009–2012, Texas Instruments Incorporated Feature/Protocol Descriptions 33
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