Datasheet

XIO2001
SCPS212G –MAY 2009–REVISED DECEMBER 2012 www.ti.com
The PCI bus clock (CLK) input provides the clock to the internal PCI bus core and serial IRQ core. When
the internal PCI bus clock source is selected, PCI bus clock output 6 (CLKOUT6) is connected to the PCI
bus clock input (CLK). When an external PCI bus clock source is selected, the external clock source is
connected to the PCI bus clock input (CLK). For external clock mode, all seven CLKOUT6:0 terminals
must be disabled using the clock control register at offset D8h (see Section 4.66).
3.5 PCI Port Arbitration
The internal PCI port arbitration logic supports up to six external PCI bus devices plus the bridge. This
bridge supports a classic PCI arbiter.
3.5.1 Classic PCI Arbiter
The classic PCI arbiter is configured through the classic PCI configuration space at offset DCh. Table 3-5
identifies and describes the registers associated with classic PCI arbitration mode.
Table 3-5. Classic PCI Arbiter Registers
PCI OFFSET REGISTER NAME DESCRIPTION
Contains a two-tier priority scheme for the bridge and six PCI bus devices. The
Classic PCI configuration Arbiter control
bridge defaults to the high priority tier. The six PCI bus devices default to the low
register DCh (see Section 4.69)
priority tier. A bus parking control bit (bit 7, PARK) is provided.
Six mask bits provide individual control to block each PCI Bus REQ input. Bit 7
(ARB_TIMEOUT) in the arbiter request mask register enables generating timeout
Classic PCI configuration Arbiter request mask status if a PCI device does not respond within 16 PCI bus clocks. Bit 6
register DDh (see Section 4.70) (AUTO_MASK) in the arbiter request mask register automatically masks a PCI bus
REQ if the device does not respond after GNT is issued. The AUTO_MASK bit is
cleared to disable any automatically generated mask.
Classic PCI configuration Arbiter time-out status When bit 7 (ARB_TIMEOUT) in the arbiter request mask register is asserted,
register DEh (see Section 4.71) timeout status for each PCI bus device is reported in this register.
3.6 Configuration Register Translation
PCI Express configuration register transactions received by the bridge are decoded based on the
transaction’s destination ID. These configuration transactions can be broken into three subcategories: type
0 transactions, type 1 transactions that target the secondary bus, and type 1 transactions that target a
downstream bus other than the secondary bus.
PCI Express type 0 configuration register transactions always target the configuration space and are never
passed on to the secondary interface.
Type 1 configuration register transactions that target a device on the secondary bus are converted to type
0 configuration register transactions on the PCI bus. Figure 3-5 shows the address phase of a type 0
configuration transaction on the PCI bus as defined by the PCI specification.
Figure 3-5. Type 0 Configuration Transaction Address Phase Encoding
In addition, the bridge converts the destination ID device number to one of the AD[31:16] lines as the
IDSEL signal. The implemented IDSEL signal mapping is shown in Table 3-6.
30 Feature/Protocol Descriptions Copyright © 2009–2012, Texas Instruments Incorporated
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