Datasheet

XIO2001
www.ti.com SCPS212G –MAY 2009–REVISED DECEMBER 2012
4.7 Primary Latency Timer Register ......................................................................................... 47
4.8 Header Type Register .................................................................................................... 47
4.9 BIST Register .............................................................................................................. 47
4.10 Device Control Base Address Register ................................................................................. 47
4.11 Primary Bus Number Register ........................................................................................... 48
4.12 Secondary Bus Number Register ....................................................................................... 48
4.13 Subordinate Bus Number Register ...................................................................................... 48
4.14 Secondary Latency Timer Register ..................................................................................... 49
4.15 I/O Base Register ......................................................................................................... 49
4.16 I/O Limit Register .......................................................................................................... 49
4.17 Secondary Status Register ............................................................................................... 50
4.18 Memory Base Register ................................................................................................... 51
4.19 Memory Limit Register .................................................................................................... 51
4.20 Prefetchable Memory Base Register ................................................................................... 51
4.21 Prefetchable Memory Limit Register .................................................................................... 52
4.22 Prefetchable Base Upper 32-Bit Register .............................................................................. 52
4.23 Prefetchable Limit Upper 32-Bit Register .............................................................................. 53
4.24 I/O Base Upper 16-Bit Register ......................................................................................... 53
4.25 I/O Limit Upper 16-Bit Register .......................................................................................... 53
4.26 Capabilities Pointer Register ............................................................................................. 54
4.27 Interrupt Line Register .................................................................................................... 54
4.28 Interrupt Pin Register ..................................................................................................... 54
4.29 Bridge Control Register ................................................................................................... 55
4.30 Capability ID Register ..................................................................................................... 57
4.31 Next Item Pointer Register ............................................................................................... 57
4.32 Subsystem Vendor ID Register .......................................................................................... 57
4.33 Subsystem ID Register ................................................................................................... 58
4.34 Capability ID Register ..................................................................................................... 58
4.35 Next Item Pointer Register ............................................................................................... 58
4.36 Power Management Capabilities Register ............................................................................. 58
4.37 Power Management Control/Status Register .......................................................................... 59
4.38 Power Management Bridge Support Extension Register ............................................................ 60
4.39 Power Management Data Register ..................................................................................... 60
4.40 MSI Capability ID Register ............................................................................................... 60
4.41 Next Item Pointer Register ............................................................................................... 61
4.42 MSI Message Control Register .......................................................................................... 61
4.43 MSI Message Lower Address Register ................................................................................. 61
4.44 MSI Message Upper Address Register ................................................................................. 62
4.45 MSI Message Data Register ............................................................................................. 62
4.46 PCI Express Capability ID Register ..................................................................................... 63
4.47 Next Item Pointer Register ............................................................................................... 63
4.48 PCI Express Capabilities Register ...................................................................................... 63
4.49 Device Capabilities Register ............................................................................................. 64
4.50 Device Control Register .................................................................................................. 65
4.51 Device Status Register ................................................................................................... 66
4.52 Link Capabilities Register ................................................................................................ 66
4.53 Link Control Register ...................................................................................................... 67
4.54 Link Status Register ....................................................................................................... 68
4.55 Serial-Bus Data Register ................................................................................................. 69
4.56 Serial-Bus Word Address Register ...................................................................................... 69
4.57 Serial-Bus Slave Address Register ..................................................................................... 70
4.58 Serial-Bus Control and Status Register ................................................................................ 70
4.59 GPIO Control Register .................................................................................................... 71
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