Datasheet

XIO2001
www.ti.com SCPS212G –MAY 2009–REVISED DECEMBER 2012
Table 3-1. XIO2001 Reset Options (continued)
RESET XIO2001 FEATURE RESET RESPONSE
OPTION
PCI Express This XIO2001 input terminal is used by an upstream PCI When PERST is asserted low, all control register bits that
reset input Express device to generate a PCI Express reset and to are not sticky are reset. Within the configuration register
PERST signal a system power good condition. maps, the sticky bits are indicated by the ☆ symbol. Also,
all state machines that are not associated with sticky
When PERST is asserted low, the XIO2001 generates an
functionality are reset.
internal PCI Express reset as defined in the PCI Express
specification.
When PERST transitions from low to high, a system power In addition, the XIO2001 asserts the internal PCI bus reset.
good condition is assumed by the XIO2001.
Note: The system must assert PERST before power is When the rising edge of PERST occurs, the XIO2001
removed, before REFCLK is removed or before REFCLK samples the state of all static control inputs and latches
becomes unstable. the information internally. If an external serial EEPROM is
detected, then a download cycle is initiated. Also, the
process to configure and initialize the PCI Express link is
started. The XIO2001 starts link training within 80 ms after
PERST is deasserted.
PCI Express The XIO2001 responds to a training control hot reset In the DL_DOWN state, all remaining configuration register
training control received on the PCI Express interface. After a training bits and state machines are reset. All remaining bits
hot reset control hot reset, the PCI Express interface enters the exclude sticky bits and EEPROM loadable bits. All
DL_DOWN state. remaining state machines exclude sticky functionality and
EEPROM functionality.
Within the configuration register maps, the sticky bits are
indicated by the ☆ symbol and the EEPROM loadable bits
are indicated by the † symbol.
In addition, the XIO2001 asserts the internal PCI bus reset.
PCI bus reset System software has the ability to assert and deassert the When bit 6 (SRST) in the bridge control register at offset
PRST PRST terminal on the secondary PCI bus interface. This 3Eh (see Section 4.29) is asserted, the bridge asserts the
terminal is the PCI bus reset. PRST terminal. A 0 in the SRST bit deasserts the PRST
terminal.
3.3 PCI Express Interface
3.3.1 External Reference Clock
The bridge requires either a differential, 100-MHz common clock reference or a single-ended, 125-MHz
clock reference. The selected clock reference must meet all PCI Express Electrical Specification
requirements for frequency tolerance, spread spectrum clocking, and signal electrical characteristics.
Spread Spectrum is an optional feature of the PCI Express Electrical Specification that is supported by
this bridge.
If the REFCLK125_SEL input is connected to V
SS
, then a differential, 100-MHz common clock reference is
expected by the XIO2001. If the REFCLK125_SEL terminal is connected to V
DD_33
, then a single-ended,
125-MHz clock reference is expected by the bridge
When the single-ended, 125-MHz clock reference option is enabled, the single-ended clock signal is
connected to the REFCLK+ terminal. The REFCLK– terminal is connected to one side of an external
capacitor with the other side of the capacitor connected to V
SS
.
When using a single-ended reference clock, care must be taken to ensure interoperability from a system
jitter standpoint. The PCI Express Base Specification does not ensure interoperability when using a
differential reference clock commonly used in PC applications along with a single-ended clock in a non-
common clock architecture. System jitter budgets will have to be verified to ensure interoperability. See
the PCI Express Jitter and BER White Paper from the PCI-SIG.
Copyright © 2009–2012, Texas Instruments Incorporated Feature/Protocol Descriptions 25
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