Datasheet

V and
DD_15
V
DDA_15
REFCLK
PERST
100 ms
100 ms
V and
DD_33
V
DDA_33
PCIR
XIO2001
www.ti.com SCPS212G –MAY 2009–REVISED DECEMBER 2012
3.1.1 Power-Up Sequence
1. Assert PERST to the device.
2. Apply 1.5-V and 3.3-V voltages.
3. Apply PCIR clamp voltage.
4. Apply a stable PCI Express reference clock.
5. To meet PCI Express specification requirements, PERST cannot be deasserted until the following two
delay requirements are satisfied:
– Wait a minimum of 100 μs after applying a stable PCI Express reference clock. The 100-μs limit
satisfies the requirement for stable device clocks by the deassertion of PERST.
– Wait a minimum of 100 ms after applying power. The 100-ms limit satisfies the requirement for
stable power by the deassertion of PERST.
See the power-up sequencing diagram in Figure 3-2.
Figure 3-2. Power-Up Sequence
Copyright © 2009–2012, Texas Instruments Incorporated Feature/Protocol Descriptions 23
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