Datasheet

XIO2001
SCPS212G –MAY 2009–REVISED DECEMBER 2012 www.ti.com
Table 2-2. Ground Terminals
SIGNAL ZGU BALL # ZAJ BALL # PNP PIN # I/O TYPE DESCRIPTION
V
SS
D04, F04, H04, E06, F05, G05, GND Digital ground terminals
K04, K05, K06, H05, J05, J06,
K08, L11, J10, J09, H09, E09,
D10, D08, D06, E08, E07, F12
F11, F12 ,F09
V
SS
E05, E06, E07, GND Ground terminals for thermally-enhanced package
E08, E09, F05,
F06, F07, F08,
F09, G05, G06,
G07, G08, G09,
H05, H06, H07,
H08, H09, J05,
J06, J07, J08,
J09
V
SSA
K10, C11, H12, G09, B12, J13, 79, 82, 86, 89 GND Analog ground terminal
G11, E11, E10 G12, F13, D12
Table 2-3. Combined Power Output Terminals
ZGU ZAJ PNP I/O EXTERNAL
SIGNAL DESCRIPTION
BALL # BALL # PIN # TYPE PARTS
V
DD_15_COMB
L13 N13 69 Internally-combined 1.5-V main and V
AUX
power
output for external bypass capacitor filtering.
Feed Bypass
Supplies all internal 1.5-V circuitry powered by V
AUX
.
through capacitors
Caution: Do not use this terminal to supply external
power to other devices.
V
DD_33_COMB
J13 K12 75 Internally-combined 3.3-V main and V
AUX
power
output for external bypass capacitor filtering.
Feed Bypass
Supplies all internal 3.3-V circuitry powered by V
AUX
.
through capacitors
Caution: Do not use this terminal to supply external
power to other devices.
V
DD_33_COMBIO
K11 K11 70 Internally-combined 3.3-V main and V
AUX
power
output for external bypass capacitor filtering.
Supplies all internal 3.3-V input/output circuitry
Feed Bypass
powered by V
AUX
.
through capacitors
Caution: Do not use this terminal to supply external
power to other devices.
Table 2-4. PCI Express Terminals
ZGU ZAJ PNP I/O CELL CLAMP EXTERNAL
SIGNAL DESCRIPTION
BALL # BALL # PIN # TYPE TYPE RAIL PARTS
CLKREQ D11 D11 91 0 LV V
DD_33_
Clock request. When asserted low, requests
CMOS
COMBIO
upstream device start clock in cases where clock
may be removed in L1.
–
Note: Since CLKREQ is an open-drain output
buffer, a system side pullup resistor is required.
PERST H11 H11 77 I LV V
DD_33_
PCI Express reset input. The PERST signal
CMOS
COMBIO
identifies when the system power is stable and
–
generates an internal power on reset.
Note: The PERST input buffer has hysteresis.
REFCLK125_SEL B13 A13 95 I LV V
DD_33
Reference clock select. This terminal selects the
CMOS reference clock input.
Pullup or
pulldown 0 = 100-MHz differential common reference clock
resistor used.
1 = 125-MHz single-ended, reference clock used.
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