Datasheet
XIO2001
www.ti.com
SCPS212G –MAY 2009–REVISED DECEMBER 2012
Table 6-9. Pre-Fetch Agent Request Limits Register Description (continued)
BIT FIELD NAME ACCESS DESCRIPTION
Request Length Limit. Determines the number of bytes in the thread that the pre-fetch
agent will read for that thread.
0000 = 64 bytes
0001 = 128 bytes
0010 = 256 bytes
PFA_REQ_LENGT
3:0 RW 0011 = 512 bytes
H_LIMIT
0100 = 1 Kbytes
0101 = 2 Kbytes
0110 = 4 Kbytes
0111 = 8 Kbytes
1000:1111 = Reserved
6.13 Cache Timer Transfer Limit Register
This register is used to set the number of PCI cycle starts that have to occur without a read hit on the
completion data buffer, before the cache data can be discarded. This register is an alias for the pre-fetch
agent request limits register in the classic PCI configuration space (offset EAh, see Section 4.76). See
Table 6-10 for a complete description of the register contents.
Device control memory window register 52h
offset:
Register type: Read/Clear
Default value: 0008h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0
Table 6-10. Cache Timer Transfer Limit Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:8 RSVD R Reserved. Returns 00h when read.
CACHE_TMR_XFR Number of PCI cycle starts that have to occur without a read hit on the completion data
7:0
(1)
RW
_LIMIT buffer, before the cache data can be discarded.
(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
6.14 Cache Timer Lower Limit Register
Minimum number of clock cycles that must have passed without a read hit on the completion data buffer
before the "cache miss limit" check can be triggered. See Table 6-11 for a complete description of the
register contents.
Device control memory window 54h
register offset:
Register type: Read/Clear
Default value: 007Fh
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1
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