Datasheet

XIO2001
SCPS212G –MAY 2009–REVISED DECEMBER 2012 www.ti.com
Table 6-7. Serial IRQ Edge Control Register Description (continued)
BIT FIELD NAME ACCESS DESCRIPTION
IRQ 3 edge mode
3
(1)
IRQ3_MODE RW
0 = Edge mode (default)
1 = Level mode
IRQ 2 edge mode
2
(1)
IRQ2_MODE RW
0 = Edge mode (default)
1 = Level mode
IRQ 1 edge mode
1
(1)
IRQ1_MODE RW
0 = Edge mode (default)
1 = Level mode
IRQ 0 edge mode
0
(1)
IRQ0_MODE RW
0 = Edge mode (default)
1 = Level mode
6.11 Serial IRQ Status Register
This register indicates when a level mode IRQ is signaled on the serial IRQ stream. After a level mode
IRQ is signaled, a write-back of 1b to the asserted IRQ status bit re-arms the interrupt. IRQ interrupts that
are defined as edge mode in the serial IRQ edge control register are not reported in this status register.
This register is an alias for the serial IRQ status register in the classic PCI configuration space (offset E4h,
see Section 4.74). See Table 4-48 for a complete description of the register contents.
Device control memory window register 4Ch
offset:
Register type: Read/Clear
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 6-8. Serial IRQ Status Register Description
BIT FIELD NAME ACCESS DESCRIPTION
IRQ 15 asserted. This bit indicates that the IRQ15 has been asserted.
15
(1)
IRQ15 RCU
0 = Deasserted
1 = Asserted
IRQ 14 asserted. This bit indicates that the IRQ14 has been asserted.
14
(1)
IRQ14 RCU
0 = Deasserted
1 = Asserted
IRQ 13 asserted. This bit indicates that the IRQ13 has been asserted.
13
(1)
IRQ13 RCU
0 = Deasserted
1 = Asserted
(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
110 Memory-Mapped TI Proprietary Register Space Copyright © 2009–2012, Texas Instruments Incorporated
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