Datasheet

XIO2001
SCPS212G –MAY 2009–REVISED DECEMBER 2012 www.ti.com
6.9 Serial IRQ Mode Control Register
This register controls the behavior of the serial IRQ controller. This register is an alias for the serial IRQ
mode control register in the classic PCI configuration space (offset E0h, see Section 4.72). See Table 4-
46 for a complete description of the register contents.
Device control memory window register 48h
offset:
Register type: Read-only, Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
Table 6-6. Serial IRQ Mode Control Register Description
BIT FIELD NAME ACCESS DESCRIPTION
7:4 RSVD R Reserved. Returns 0h when read.
Start frame pulse width. Sets the width of the start frame for a SERIRQ stream.
00 = 4 clocks (default)
3:2
(1)
START_WIDTH RW
01 = 6 clocks
10 = 8 clocks
11 = Reserved
Poll mode. This bit selects between continuous and quiet mode.
1
(1)
POLLMODE RW
0 = Continuous mode (default)
1 = Quiet mode
RW Drive mode. This bit selects the behavior of the serial IRQ controller during the
recovery cycle.
0
(1)
DRIVEMODE RW
0 = Drive high (default)
1 = 3-state
(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
6.10 Serial IRQ Edge Control Register
This register controls the edge mode or level mode for each IRQ in the serial IRQ stream. This register is
an alias for the serial IRQ edge control register in the classic PCI configuration space (offset E2h, see
Section 4.73). See Table 6-7 for a complete description of the register contents.
Device control memory window register 4Ah
offset:
Register type: Read/Write
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
108 Memory-Mapped TI Proprietary Register Space Copyright © 2009–2012, Texas Instruments Incorporated
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