Datasheet

XIO2001
www.ti.com SCPS212G –MAY 2009–REVISED DECEMBER 2012
6 Memory-Mapped TI Proprietary Register Space
The programming model of the memory-mapped TI proprietary register space is unique to this device.
All bits marked with a ☆ are sticky bits and are reset by a global reset (GRST) or the internally-generated
power-on reset. All bits marked with a
(2)
are reset by a PCI Express reset (PERST), a GRST or the
internally-generated power-on reset. The remaining register bits are reset by a PCI Express hot reset,
PERST, GRST, or the internally-generated power-on reset.
Table 6-1. Device Control Memory Window Register Map
REGISTER NAME OFFSET
Reserved Revision ID Device control map ID 000h
Reserved 004h–03Ch
GPIO data
(1)
GPIO control
(1)
040h
Serial-bus control and status
(1)
Serial-bus slave address
(1)
Serial-bus word address
(1)
Serial-bus data
(1)
044h
Serial IRQ edge control
(1)
Reserved Serial IRQ mode 048h
control
(1)
Reserved Serial IRQ status
(1)
04Ch
Cache Timer Transfer Limit
(1)
PFA Request Limit
(1)
050h
Cache Timer Upper Limit
(1)
Cache Timer Lower Limit
(1)
054h
Reserved 058h–FFFh
(2) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
(1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
6.1 Device Control Map ID Register
The device control map ID register identifies the TI proprietary layout for this device control map. The
value 04h identifies this as a PCI Express-to-PCI bridge.
Device control memory window register offset: 00h
Register type: Read-only
Default value: 04h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 1 0 0
Copyright © 2009–2012, Texas Instruments Incorporated Memory-Mapped TI Proprietary Register Space 103
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