Datasheet

XIO2001

SCPS212G –MAY 2009–REVISED DECEMBER 2012

www.ti.com

2 Overview

The Texas Instruments XIO2001 is a PCI Express to PCI local bus translation bridge that provides full PCI

Express and PCI local bus functionality and performance.

2.1 Description

The XIO2001 is a single-function PCI Express to PCI translation bridge that is fully compliant to the PCI

Express to PCI/PCI-X Bridge Specification, Revision 1.0. For downstream traffic, the bridge

simultaneously supports up to eight posted and four non-posted transactions. For upstream traffic, up to

six posted and and four non-posted transactions are simultaneously supported.

The PCI Express interface is fully compliant to the PCI Express Base Specification, Revision 2.0.

The PCI Express interface supports a ×1 link operating at full 250 MB/s packet throughput in each

direction simultaneously. Also, the bridge supports the advanced error reporting including extended CRC

(ECRC) as defined in the PCI Express Base Specification. Supplemental firmware or software is required

to fully utilize both of these features.

Robust pipeline architecture is implemented to minimize system latency across the bridge. If parity errors

are detected, then packet poisoning is supported for both upstream and downstream operations.

The PCI local bus is fully compliant with the PCI Local Bus Specification (Revision 2.3) and associated

programming model. Also, the bridge supports the standard PCI-to-PCI bridge programming model. The

PCI bus interface is 32-bit and can operate at either 25 MHz, 33 MHz, 50 MHz, or 66 MHz. Also, the PCI

interface provides fair arbitration and buffered clock outputs for up to 6 subordinate devices.

Power management (PM) features include active state link PM, PME mechanisms, the beacon and wake

protocols, and all conventional PCI D-states. If the active state link PM is enabled, then the link

automatically saves power when idle using the L0s and L1 states. PM active state NAK, PM PME, and

PME-to-ACK messages are supported. Standard PCI bus power management features provide several

low power modes, which enable the host system to further reduce power consumption.

The bridge has additional capabilities including, but not limited to, serial IRQ with MSI messages, serial

EEPROM, power override, clock run, PCI Express clock request and PCI bus LOCK. Also, five general-

purpose inputs and outputs (GPIOs) are provided for further system control and customization.

2.2 Related Documents

• PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0

• PCI Express Base Specification, Revision 2.0

• PCI Express Card Electromechanical Specification, Revision 2.0

• PCI Local Bus Specification, Revision 2.3

• PCI-to-PCI Bridge Architecture Specification, Revision 1.2

• PCI Bus Power Management Interface Specification, Revision 1.2

• PCI Mobile Design Guide, Revision 1.1

• Serialized IRQ Support for PCI Systems, Revision 6.0

Submit Documentation Feedback

Product Folder Links: XIO2001