Datasheet

Description

June 2006 Revised August 2011SLLS690C

2.6 Receiver Detection

While in the P1 power state, XIO1100 can be instructed to perform a receiver detection operation to determine

if there is a receiver at the other end of the link. The MAC requests XIO1100 to do a receiver detect sequence

by asserting TXDETECTRX/LOOPBACK high. Upon completion of the receiver detection operation, the

XIO1100 asserts PHY_STATUS high for one RX_CLK cycle. While PHY_STATUS is high, XIO1100 drives the

proper receiver status code onto the RX_STATUS[2:0] signals according to Table 2−2. After the receiver

detection has completed (as signaled by the assertion of PhyStatus), the MAC must de−assert

TxDetectRx/Loopback before initiating another receiver detection or a power state transition.

Table 2−2. RX_STATUS Loopback Detection Code

RX_STATUS[2:0] RECEIVER STATUS

000 Receiver not present

011 Receiver present

NOTE: TX_DET_LOOPBACK must remain asserted until XIO1100 asserts the PHY_STATUS.

2.7 Receiver Clock Tolerance Compensation

The XIO1100 receiver contains an elastic buffer that compensates for differences in frequencies between bit

rates at the two ends of a link. The elastic buffer is capable of holding at least seven symbols to tolerate

worst-case differences (600ppm) in frequency and worst-case intervals between SKP ordered-sets, where

an SKP order-set is a set of symbols transmitted as a group. The first symbol of a SKP ordered-set is a COM

(0xBC) and is followed by three SKP (0x1C) symbols. The purpose of SKP ordered-sets is to allow the

receiving device (in this case, XIO1100) to adjust the data stream that is being received to prevent the elastic

buffer from either overflowing or underflowing due to any differences between the clocking frequencies of the

transmitting device and the receiving device. The XIO1100 monitors the data stream received at the RXP/RXN

differential pair for SKP ordered-sets.

When the XIO1100 detects that an SKP ordered-set is being received, it either adds or removes SKP symbols

from the data stream, depending on the current state of the elastic buffer. If the elastic buffer is in danger of

underflowing, SKP symbols are added to the ordered-set before it is loaded into the buffer. If the elastic buffer

is in danger of overflowing, SKP symbols are removed from the ordered-set before it is loaded into the buffer.

When the XIO1100 detects a SKP ordered-set, the XIO1100 asserts an Add SKP code (001b) on the

RX_STATUS[2:0] bus in the same RX_CLK cycle that it asserts the COM (0xBC) symbol on the

RX_DATA[15:0] bus, if it is adding a SKP symbol to the data stream. In the case of removing an SKP symbol,

the XIO1100 asserts the Remove SKP code (010b) to the RX_STATUS[2:0] when the COM symbol is

asserted.

2.8 Error Detection

If a detectable receive error occurs, the appropriate error code is asserted on the RX_STATUS[2:0] pins for

one RX_CLK cycle as close as possible to the point in the data stream where the error occurred. There are

four error conditions that can be encoded on the RXSTATUS signals. If more than one error happens to occur

on a received byte (or set of bytes transferred across a 16-bit interface), the errors are signaled with the

following priority:

• 8B/10B decode error

• Elastic buffer overflow

• Elastic buffer underflow

• Disparity error

If an error occurs during a SKP ordered-set, such that the error code and the SKP code occur concurrently,

the error code has priority over the SKP code.