Datasheet

Description
3
June 2006 Revised August 2011 SLLS690C
2.3.1 P0
P0 is the normal operation state for the XIO1100. The POWERDOWN[1:0] input signals define which of the
three power states that an XIO110 is in at any given time. In states P0, P0s, and P1, the XIO1100 is required
to keep P_CLK operational. For all state transitions between these three states, the XIO1100 indicates
successful transition into the designated power state by a single cycle assertion of PHY_STATUS. For all
power state transitions, the MAC must not begin any operational sequence or more power state transitions
until the XIO1100 has indicated that the initial state transition is finished. P2 state and beacon are not
supported.
In the P0 state, all internal clocks in the XIO1100 are operational. P0 is the only state where the XIO1100
transmits and receives PCI Express signaling. P0 is the appropriate PHY power management state for most
states in the Link Training and Status State Machine (LTSSM). Exceptions are listed as follows for each lower
power XIO1100 state.
2.3.2 P0s
In the P0s state, RX_CLK output stays operational. The MAC moves the XIO1100 to this state only when the
transmit channel is idle. P0s state is used when the transmitter is in state Tx_L0s.Idle. If the receiver detects
an electrical idle while the XIO1100 is in either P0 or P0s power states, the receiver portion of the XIO1100
takes appropriate power saving measures.
2.3.3 P1
In the P1 state, selected internal clocks in the XIO1100 will be turned off. RX_CLK output will stay operational.
The MAC moves the XIO1100 to this state only when both transmit and receive channels are idle. The
XIO1100 does not indicate successful entry into P1 (by asserting PhyStatus) until RX_CLK is stable and the
operating dc common mode voltage is stable and within specification (in accordance with PCI Express Base
Specification). P1 is used for the Disabled state, all Detect states, and L1.Idle state of the Link Training and
Status State Machine (LTSSM). While in P1 state, the optional P1_SLEEP input signal can be used to reduce
even more power consumption by disabling the RX_CLK signal. However, the P1_SLEEP input must not be
asserted when the XIO1100 is in any state other than P1 state, and the XIO1100 must not be transitioned out
of the P1 state as long as P1_SLEEP is asserted.
2.4 Clock
The RX_CLK of XIO1100 is derived from the REFCLK input. A 100 MHz differential clock or a 125 MHz single
ended clock can be used as the source clock. The frequency selection is determined by CLK_SEL. If
CLK_SEL is low during /RESET transitioning from a low state to a high state, the source clock at
REFCLK+/REFCLK− is a 100 MHz differential clock. If CLK_SEL is high during /RESET transitioning from a
low state to a high state, the source clock at REFCLK+ is a 125 MHz single ended clock. In this case, REFCLK−
needs to be tied to VSS.
Table 2−1. Clock Selection
RX_CLK
CLK_SEL = 0 100 MHz differential clock
CLK_SEL = 1 125 MHz single ended clock
2.5 Reset
When the MAC resets the XIO1100 (initial power on), the MAC must hold the XIO1100 in reset until power
and REFCLK to the XIO1100 are stable. The XIO1100 signals that RX_CLK is valid (RX_CLK has been
running at its operational frequency for at least one clock), and the XIO1100 is in the specified power state
by the de−assertion of PhyStatus. While Reset# is asserted, the MAC must have TxDetectRx/Loopback
de−asserted, TxElecIdle asserted, TxCompliance de−asserted, RxPolarity de−asserted, and PowerDown =
P1.