Datasheet

Description
2
June 2006 Revised August 2011SLLS690C
2.2 Functional Description
The XIO1100 meets all of the requirements for a PCI−Express PHY as defined by Section 4, Physical Layer
Specifications, of the PCI−SIG document PCI Express Base Specification. The XIO1100 conforms to the
functional behavior described in PHY Interface for the PCI Expresst Architecture by Intel Corporation. There
are only two differences between the XIO1100 TI−PIPE interface and the Intel PIPE interface.
The PIPE interface uses a single SDR clock source to clock both the RXDATA and the TXDATA. The TI−PIPE
interface uses two source synchronous clocks, RX_CLK and TX_CLK, to clock the RXDATA and TXDATA.
RXDATA uses RX_CLK and TXDATA uses TX_CLK.
In the 8-bit mode, the TI−PIPE interface is a DDR (Double Data Rate) interface. In the 16-bit mode, it is an
SDR (Single Data Rate) interface. The PIPE interface is always an SDR interface.
Figure 2−1 shows a functional block diagram of the XIO1100.
PLL
REFCLK/REFCLK−
TX BLOCK
TX_DATA 16/8
TX_DATAK[1:0]
TXP/TXN
RXP/RXNRX_DATA 16/8
RX_DATAK[1:0]
COMMAND
RX BLOCK
STATUS
RX_CLK
TX_CLK
Figure 2−1. XIO1100 Functional Block Diagram
2.3 Power Management
The three power states are:
• P0
• P0s
• P1