Datasheet

Application Information
28
June 2006 Revised August 2011SLLS690C
The XIO1100 is optimized for this type of system clock design. The REFCLK+ and REFCLK− terminals provide
differential reference clock inputs to the XIO1100. The circuit board routing rules associated with the 100-MHz
differential reference clock are the same as the 2.5-Gb/s TX and RX link routing rules already described. The
only difference is that the differential reference clock does not require series capacitors. The requirement is
a dc connection from the clock driver output to the XIO1100 receiver input.
Terminating the differential clock signal is circuit−board−design specific. However, the XIO1100 design has
no internal 50-Ω−to−ground termination resistors. Both REFCLK inputs, which are at approximately 20 kΩ to
ground, are high−impedance inputs.
The second option is a 125-MHz asynchronous single-ended reference clock. For this case, the devices at
each end of the PCI Express link have different clock sources. The XIO1100 has a 125-MHz single-ended
reference clock option for asynchronous clocking designs. When the CLK_SEL input terminal is tied to VSS,
this clocking mode is enabled.
The single-ended reference clock is attached to the REFCLK+ terminal. The REFCLK+ input, which is at
approximately 20 kΩ, is a high-impedance input. Any clock termination design must account for a
high-impedance input. The REFCLK− terminal needs to be attached to VSS.
5.5 PIPE Interface Layout Guidelines
The XIO1100 PIPE interface can operate at either 125 MHz or 250 MHz, depending on the state of the
DDR_EN pin. Due to the high frequencies, high-speed design techniques should be employed. When routing
the PIPE interface, the following circuit board design guidelines must be considered:
1. Due to the synchronous clock design of the XIO1100, the TX_DATA path and the RX_DATA path do not
require a matched length with respect to each other.
2. The TX_DATA path signals should be length matched to each other. The tolerance is dependent on the
setup/hold times for both the FPGA or ASIC and the XIO1100.
3. The RX_DATA path signals should be length matched to each other. The tolerance is dependent on the
setup/hold times for both the FPGA or ASIC and the XIO1100.
4. Because of the edge rates of the PIPE interface (0.9 ns rise and fall time at a 10 pF load), it is important
to keep the traces as short as possible. It is recommended to keep the trace length below 2.5 inches
(assuming FR4 and a velocity of 172 ps per inch) to reduce the effect of crosstalk. Obviously, increasing
the edge-to-edge spacing of the traces also reduces the effect of crosstalk.
5. In cases where the trace length is long and/or goes through a connector, it is recommended to use series
termination resistors on each PIPE signal. These resistors need to be placed as close as possible to the
source (resistors for the RX_DATA path next to the XIO1100 and resistors for the TX_DATA path next to
the FPGA or ASIC). The value of the series termination resistor depends on the impedance (Z
o
) of the
trace. Normally, the value of this resistor is Z
o
minus the output impedance of the driver. For the XIO1100,
the output impedance of the RX_DATA path is 25-Ω (typ).
It is recommended to model your design before going to fabrication. An I/O Buffer Information Specification
(IBIS) model of the XIO1100 is available upon request.