Datasheet

Application Information
27
June 2006 Revised August 2011 SLLS690C
5.4 PCIe Layout Guidelines
The XIO1100 TXP and TXN terminals comprise a low-voltage, 100-Ω differentially driven signal pair. The RXP
and RXN terminals for the XIO1100 receive a low-voltage, 100-Ω differentially driven signal pair. The XIO1100
has integrated 50-Ω termination resistors to VSS on both the RXP and RXN terminals, eliminating the need
for external components.
Each lane of the differential signal pair must be ac-coupled. The recommended value for the series capacitor
is 0.1 μF. To minimize stray capacitance associated with the series capacitor circuit board solder pads,
0402-sized capacitors are recommended.
When routing a 2.5-Gb/s low-voltage, 100-Ω differentially driven signal pair, the following circuit board design
guidelines must be considered:
1. The PCI Express drivers and receivers are designed to operate with adequate bit error rate margins over
a 20” maximum length signal pair routed through FR4 circuit board material.
2. Each differential signal pair must be 100-Ω differential impedance with each single-ended lane measuring
in the range of 50-Ω to 55-Ω impedance to ground.
3. The differential signal trace lengths associated with a PCI Express high-speed link must be length
matched to minimize signal jitter. This length-matching requirement applies only to the P and N signals
within a differential pair. The transmitter differential pair does not need to be length matched to the receiver
differential pair. The absolute maximum trace length difference between the TXP signal and TXN signal
must be less than 5 mils. This value also applies to the RXP and RXN signal pair.
4. If a differential signal pair is broken into segments by vias, series capacitors, or connectors, the length
of the positive signal trace must be length matched to the negative signal trace for each segment. Trace
length differences over all segments are additive and must be less than 5 mils.
5. The location of the series capacitors is critical. For add-in cards, the series capacitors are located between
the TXP/TXN terminals and the PCI Express connector. In addition, the capacitors are placed near the
PCI Express connector. This translates to two capacitors on the motherboard for the downstream link,
and two capacitors on the add-in card for the upstream link. If both the upstream device and the
downstream device reside on the same circuit board, the capacitors are located near the TXP/TXN
terminals for each link.
6. The number of vias must be minimized. Each signal trace via reduces the maximum trace length by
approximately 2 inches. For example: if 6 vias are needed, the maximum trace length is 8 inches.
7. When routing a differential signal pair, 45-degree angles are preferred over 90-degree angles. Signal
trace length matching is easier with 45-degree angles, and overall signal trace length is reduced.
8. The differential signal pairs must not be routed over gaps in the power planes or ground planes. This
causes impedance mismatches.
9. If vias are used to change from one signal layer to another signal layer, it is important to maintain the same
50-Ω impedance reference to the ground plane. Changing reference planes causes signal trace
impedance mismatches. If changing reference planes cannot be prevented, bypass capacitors
connecting the two reference planes next to the signal trace vias help reduce the impedance mismatch.
If possible, the differential signal pairs must be routed on the top and bottom layers of a circuit board. Signal
propagation speeds are faster on external signal layers.
The XIO1100 supports two options for the PCI Express reference clock: a 100-MHz common differential
reference clock or a 125-MHz asynchronous single-ended reference clock. Both implementations are
described.
The first option is a system-wide 100-MHz differential reference clock. A single clock source with multiple
differential clock outputs is connected to all PCI Express devices in the system. The differential connection
between the clock source and each PCI Express device is point−to−point. This system implementation is
referred to as a common clock design.