Datasheet

Application Information
25
June 2006 Revised August 2011 SLLS690C
5.2 XIO1100 Component Placement
The filter network on VDD_33_COMB, VDD_33_COMB_IO, and VDD_15_COMB needs to be placed as
close as possible to each pin (specifically H11, L13, and L12). It is recommended that the trace width for these
three pins be at least 10 mils.
The R0 and R1 terminals connect to an external resistor to set the drive current for the PCI Express TX driver.
The recommended resistor value is 14,560-Ω with 1% tolerance. A 14,560-Ω resistor is a custom value. To
eliminate the need for a custom resistor, two series resistors are recommended: a 5,900-Ω 1% resistor and
an 8,660-Ω 1% resistor. Trace lengths must be kept short to minimize noise coupling into the reference resistor
terminals.
5.3 Power Supply Filtering Recommendations
To meet the PCI Express jitter specifications, low-noise power supplies are required on several of the XIO1100
voltage terminals. The power terminals that require low-noise power include VDDA_15 and VDDA_33. This
section provides guidelines for the filter design to create low-noise power sources.
The least expensive solution for low-noise power sources is to filter existing 3.3 V and 1.5 V power supplies.
This solution requires analysis of the noise frequencies present on the power supplies. The XIO1100 has
external interfaces operating at clock rates of 100 MHz, 125 MHz, 250 MHz, and 2.5 GHz. Other devices
located near the XIO1100 may produce switching noise at different frequencies. Also, the power supplies that
generate the 3.3 V and 1.5 V power rails may add low frequency ripple noise. Linear regulators have feedback
loops that typically operate in the 100 kHz range. Switching power supplies typically have operating
frequencies in the 500 kHz range. When analyzing power supply noise frequencies, the first, third, and fifth
harmonic of every clock source should be considered.
Critical analog circuits within the XIO1100 must be shielded from this power-supply noise. The fundamental
requirement for a filter design is to reduce power-supply noise to a peak-to-peak amplitude of less than 25 mV.
This maximum noise amplitude should apply to all frequencies from 0 Hz to 12.5 GHz.
The following information should be considered when designing a power supply filter:
1. Ideally, the series resonance frequency for each filter component should be greater than the fifth harmonic
of the maximum clock frequency. With a maximum clock frequency of 1.25 GHz, the third harmonic is
3.75 GHz and the fifth harmonic is 6.25 GHz. Finding inductors and capacitors with a series resonance
frequency above 6.25 GHz is both difficult and expensive. Components with a series resonance frequency
in the 4 to 6 GHz range are a good compromise.
2. The inductor(s) associated with the filter must have a dc resistance low enough to pass the required
current for the connected power terminals. The voltage drop across the inductor must be low enough to
meet the minus 10% voltage margin requirement associated with each XIO1100 power terminal. Power
supply output voltage variation must be considered, as well as voltage drops associated with any
connector pins and circuit board power distribution geometries.
3. The Q versus frequency curve associated with the inductor must be appropriate to reduce power terminal
noise to less than the maximum peak−to−peak amplitude requirement for the XIO1100. Recommending
a specific inductor is difficult, because every system design is different and therefore the noise frequencies
and noise amplitudes are different. Many factors influence the inductor selection for the filter design.
Power supplies must have adequate input and output filtering. A sufficient number of bulk and bypass
capacitors is required to minimize switching noise. Assuming that board level power is properly filtered
and minimal low frequency noise is present, frequencies less than 10 MHz, an inductor with a Q greater
than 20 from approximately 10 MHz to 3 GHz should be adequate for most system applications.
4. The series component(s) in the filter may either be an inductor or a ferrite bead. Testing has been
performed on both component types. When measuring PCI Express link jitter, the inductor or ferrite bead
solutions produce equal results. When measuring circuit board EMI, the ferrite bead is a superior solution.