Datasheet

Timing Diagrams
22
June 2006 Revised August 2011SLLS690C
RxValid
PhyStatus
RxElecIdle
RxStatus[2:0]
RxData[7:0] (DDR mode)
RxDataK[0] (DDR mode)
TI−PIPE Output Functional Timing
RX_CLK
RxData[15:0] (SDR mode)
RxDataK[1:0] (SDR mode)
SYMBOL (N) SYMBOL (N+1)
RxData[7:0] − SYMBOL (N)
RxData[15:8] − SYMBOL (N+1)
Figure 4−3. TI−PIPE Output Functional Timing