Datasheet

Timing Diagrams
21
June 2006 Revised August 2011 SLLS690C
t
rco
t
fh
t
cyc
RX_CLK
RxData[7:0] (DDR mode)
RxDataK[0] (DDR mode)
t
rco
RxData[15:0] (SDR mode)
RxDataK[1:0] (SDR mode)
RxValid
PhyStatus
RxElecIdle
RxStatus[2:0]
TI−PIPE Data Output Timing
t
fco
t
fh
t
fh
Figure 4−2. TI−PIPE Data Output Timing
PARAMETER DESCRIPTION VALUE
tcyc Period, RX_CLK 8.0 ns (TYP)
trco Clock to output, RX_CLK rising 2.0 ns (MAX)
trh Output hold, RX_CLK rising 0.7 ns (MIN)
tfco Clock to output, RX_CLK falling 2.0 ns (MAX)
tfh Output hold, RX_CLK falling 0.7 ns (MIN)