Datasheet

Timing Diagrams
20
June 2006 Revised August 2011SLLS690C
4 Timing Diagrams
t
fsu
t
fh
t
rsu
t
cyc
TX_CLK
TxData[7:0] (DDR mode)
TxDataK[0] (DDR mode)
t
rsu
TxData[15:0] (SDR mode)
TxDataK[1:0] (SDR mode)
TxDetectRx/Loopback
TxElecIdle
TxCompliance
RxPolarity
PowerDown[1:0]
TI−PIPE Input Timing
t
fh
t
fh
Figure 4−1. TI−PIPE Input Timing
PARAMETER DESCRIPTION VALUE
tcyc Period, TX_CLK 8 ns (TYP)
trsu Input Setup to TX_CLK rising 1.3 ns (MAX)
trh Input Hold from TX_CLK rising 0.1 ns (MIN)
tfsu Input Setup to TX_CLK falling 1.3 ns (MAX)
tfh Input Hold from TX_CLK falling 0.1 ns (MIN)