Datasheet

Electrical Characteristics
19
June 2006 Revised August 2011 SLLS690C
3.6 Electrical Characteristics Over Recommended Operating Conditions (V
DD_IO
)
PARAMETER OPERATION
TEST
CONDITIONS
MIN TYP MAX UNIT
V
IH
High-level input voltage (Note 16) V
DD_IO
0.7 V
DD_IO
V
DD_IO
V
V
IL
Low-level input voltage (Note 16) V
DD_IO
0 0.3 V
DD_IO
V
V
I
Input voltage 0 V
DD_IO
V
V
O
Output voltage (Note 17) 0 V
DD_IO
V
t
T
Input transition time (t
rise
and t
fall
) 0 25 ns
V
OH
High-level output voltage V
DD_IO
I
OH
= −8 mA 0.8 V
DD_IO
V
V
OL
Low-level output voltage V
DD_IO
I
OL
= 8 mA 0.22 V
DD_IO
V
I
OH
High−level output current −8 mA
I
OL
Low−level output current 8 mA
I
OZ
High-impedance, output current
(Note 17)
V
DD_IO
V
I
= 0 to V
DD_IO
±20 μA
I
I
Input current (Note 18) V
DD_IO
V
I
= 0 to V
DD_IO
±1 μA
NOTES: 16. Applies to external inputs and bidirectional buffers.
17. Applies to external outputs and bidirectional buffers.
18. Applies to external input buffers.
3.7 Implementation−Specific Timing
TIMING DESCRIPTION NORM MAX
Transmit
Latency
Time for data moving between the parallel interface and the PCI Express serial lines. Timing is
measured from when the data is transferred across the parallel interface (i.e., the rising edge of
TX_CLK) and when the first bit of the equivalent 10−bit symbol is transmitted on the Tx+/Tx−
serial lines.
29.2 ns 33.2 ns
Receive
Latency
Time for data moving between the parallel interface and the PCI Express serial lines. Timing is
measured from when the first bit of a 10−bit symbol is available on the Rx+/Rx− serial lines to
when the corresponding 8−bit data is transferred across the parallel interface (i.e., the rising
edge of RX_CLK).
77.2 ns 93.2 ns
Loopback
Enable Latency
Amount of time that the XIO1100 requires to begin looping back receive data. Duration is from
when TxDetectRx/Loopback is asserted until the receive data is being transmitted on the serial
pins.
25.2 ns 29.2 ns
N_FTS with
Common Clock
Number of FTS ordered sets required by the receiver to obtain reliable bit and symbol lock when
operating with a common clock.
23 23
N_FTS without
Common Clock
Number of FTS ordered sets required by the receiver to obtain reliable bit and symbol lock when
operating without a common clock.
255 255
XIO1100 Lock
Time
Amount of time required for the XIO1100 receiver to obtain reliable bit and symbol lock after
valid TSx ordered−sets are present at the receiver.
2.0 μs 4.0 μs
P0s to P0
Transitioning
Time
Amount of time required for the XIO1100 to return to the P0 state after having been in the P0s
state. Time is measured from when the MAC sets the PowerDown signals to P0 until the
XIO1100 asserts PhyStatus. The XIO1100 asserts PhyStatus when it is ready to begin data
transmission and reception.
28.0 ns 32.0 ns
P1 to P0
Transitioning
Time
Amount of time required for the XIO1100 to return to the P0 state after having been in the P1
state. Time is measured from when the MAC sets the PowerDown signals to P0 until the
XIO1100 asserts PhyStatus. The XIO1100 asserts PhyStatus when it is ready to begin data
transmission and reception.
28.0 ns 32.0 ns
Reset to Ready
Time
Timed from when Reset# is de−asserted until the XIO1100 de−asserts PHY_STATUS. 10.0 ns 11.0 ns