Datasheet

Electrical Characteristics
18
June 2006 Revised August 2011SLLS690C
3.5 Express Differential Reference Clock Input Ranges
PARAMETER TERMINALS MIN NOM MAX UNIT COMMENTS
f
IN–DIFF
Differential input fre-
quency
REFCLK+
REFCLK−
100 MHz The input frequency is 100 MHz + 300 ppm and
− 2800 ppm including SSC–dictated variations.
f
IN–SE
Single–ended input
frequency
REFCLK+ 125 MHz The input frequency is 125 MHz + 300 ppm and
− 300 ppm.
V
RX–DIFFp–p
Differential input
peak–to–peak voltage
REFCLK+
REFCLK−
0.175 1.200 V V
RX–DIFFp–p
= 2*|V
REFCLK+
− V
REFCLK−
|
V
IH–SE
REFCLK+ 0.7 V
DD_33
V
DD_33
V Single–ended, reference clock mode high-level
input voltage
V
IL–SE
REFCLK+ 0 0.3 V
DD_33
V Single–ended, reference clock mode low-level
input voltage
V
RX–CM–ACp
AC peak common
mode input voltage
REFCLK+
REFCLK−
140 mV V
RX–CM–ACp
= RMS(|V
REFCLK+
+ V
REFCLK−
|/2 –
V
RX–CM–DC
)
V
RX–CM–DC
= DC
(avg)
of |V
REFCLK+
+ V
REFCLK−
|/2
Duty cycle REFCLK+
REFCLK−
40% 60% Differential and single–ended waveform input duty
cycle
Z
RX–DIFF–DC
DC differential input
impedance
REFCLK+
REFCLK−
20 kΩ REFCLK+/− dc differential mode impedance
Z
RX–DC
DC input impedance
REFCLK+
REFCLK−
20 kΩ REFCLK+ dc single–ended mode impedance
NOTE 15: The XIO1100 is compliant with the defined system jitter models for a PCI–Express reference clock and associated TX/RX link. These
system jitter models are described in the PCI–Express Jitter Modeling, Revision 1.0RD document. Any usage of the XIO1100 in a system
configuration that does not conform to the defined system jitter models requires the system designer to validate the system jitter budgets.