Datasheet

Description
8
June 2006 Revised August 2011SLLS690C
2.14 Terminal Descriptions
Table 2−5 describes the XIO1100 terminals. The terminals are grouped by functionality.
Table 2−5. XIO1100 Terminals
TERMINAL I/O DESCRIPTION
NAME NO.
PIPE INTERFACE
/RESET N11 I Reset the device. This signal is active low and asynchronous.
POWERDOWN[1:0] L9, M9 I Power State Control:
Value: Description
00: P0, normal operation (used for all Polling, Configuration, Recovery, Loop−back,
and Hot-Reset states, and the L0 state of the LTSSM)
01: P0s, low recovery time latency, power−saving state (used for the TX_L0s.idle
state of the LTSSM)
10: P1, longer recovery time (64μs max) latency, lower power state (used for the
disabled state, all detect states, and the L1.idle state of the LTSSM)
PHY_STATUS N10 O Used to communicate completion of several PHY functions, including power
management state transitions and receiver detection
TX_CLK M8 I Synchronous input clock for TX_DATA[15:0] and TX_DATAK[1:0] inputs
If the DDR_EN signal is low during /RESET transitioning from a low state to a high
state, TX_CLK is a SDR clock and TX_DATA[15:0] and TX_DATAK[1:0] are latched
on the rising edge of TX_CLK.
If the DDR_EN signal is high during /RESET transitioning from a low state to a high
state, TX_CLK is a DDR clock and TX_DATA[7:0] and TX_DATAK[0] are latched on
both the rising and the falling edge of TX_CLK.TX_DATA[15:8] and TX_DATAK[1]
are not used.
TX_DATA[15:0] G2, H2, H1, J2,
J1, K2, K1, L1,
N3, M3, M4,
N4, M5, N5,
M6, N6
I Parallel Data Transmit Bus
If the DDR_EN signal is low during /RESET transitioning from a low state to a high
state, TX_DATA[15:0] is latched off the bus on the rising edge of TX_CLK.
TX_DATA[7:0] represents the first symbol and TX_DATA[15:8] represents the
second symbol to be transmitted over the TXN and TXP differential signal pair.
If the DDR_EN signal is high during /RESET transitioning from a low state to a high
state, TX_DATA[7:0] is latched off the bus on both edges of the TX_CLK.
TX_DATA[15:8] is not used and should be grounded. The data on TX_DATA[7:0]
during the rising edge of the clock represents the first symbol and data on
TX_DATA[7:0] during the falling edge of the clock represents the second symbol to
be transmitted over the TXN and TXP differential signal pair.
TX_DATAK[1:0] M7, N7 I Data/Control for the Parallel Data Transmit Bus
If the DDR_EN signal is low during /RESET transitioning from a low state to a high
state, TX_DATAK[0] corresponds to the TX_DATA[7:0] and TX_DATAK[1] to
TX_DATA[15:8].
If the DDR_EN signal is high during /RESET transitioning from a low state to a high
state, the state of TX_DATAK[0] corresponds to the data on the TX_DATA[7:0] bus
during the same phase of the clock. TX_DATAK[1] is not used and should be
grounded.
A value of zero indicates that the corresponding TXDATA bits contain data
information; a value of one indicates that the corresponding TXDATA bits contain a
control byte.
NOTE: The TI−PIPE interface can operate at either 1.5 V or 1.8 V, depending on the voltage level of V
DD_IO
. If V
DD_IO
is 1.5 V, the TI−PIPE
interface operates at 1.5 V level. If V
DD_IO
is 1.8 V, the TI−PIPE interface operates at 1.8 V level.