Datasheet

SLVL003
-
- Sequencing: Although Xilinx FPGAs do NOT require it, this reference design
employs sequencing. This practice is consistent with good power supply design
and prevents the input power supply from being pulled down due to supporting
in-rush currents for charging large capacitive loads.
-
- Additional Capacitance:
o The TPS54110’s have been compensated to allow for up to the following
additional capacitance on each rail:
§ 12 uF in ceramics in parallel with
§ two 330 uF capacitors, each with ESR between 0.1 and 2 ohms.
If more bypass capacitance or bulk capacitors with ESR outside the range
above is used, each TPS54x10 control loop may need to be re-
compensated using the SWIFT design software.
-
- V
CCAUX
: V
CCAUX
powers time-critical resources in the FPGA, including the
Digital Clock Managers (DCMs). Therefore, this supply voltage is especially
susceptible to power supply noise. V
CCAUX
can share a power plane with V
CCO
,
but only if V
CCO
does not have excessive noise. Changes in V
CCAUX
voltage
beyond 200 mV peak-to-peak should take place no faster than 10 mV per milli-
second.
-
- Modifications:
o Adapt for V
IN
= 3.3 V by omitting U3.
QUESTIONS?
-
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