Datasheet

SLVL005
-
- Power Dissipation/Thermal Issues: The dual regulator, U2, is limited to 2W @
T
A
= 55
o
C and no airflow, due to power dissipation limitation of the
PowerPAD
TM
package.
o Refer to the application section of the datasheet for maximum power
dissipation at different ambient conditions and guidance on sizing the
ground plane area underneath the package for heatsinking.
o The following equation can be used to solve for the maximum current on
one rail if the other rail current is known:
P
Dmax
= (V
IN
– V
CCINT
) * I
CCINTmax
+ (V
IN
– V
CCAUX
)*I
CCAUXmax
As an example, with V
IN
= 3.3 V, V
CCINT
= 1.2V, V
CCAUX
= 2.5 V, P
Dmax
=
2 W and assuming that the I
CCAUXmax
= 250 mA:
§ I
CCINT
max = [P
Dmax
- (V
IN
– V
CCAUX
) * I
CCAUXmax
]/ (V
IN
– V
CCINT
)
§ I
CCINTmax
= 857 mA
-
- Soft Start Circuitry:
o NMOS transistor Q1 should be selected so that its threshold voltage, V
TH
,
is at least 0.9 V below V
IN
or lower (e.g., V
TH
< 3.3 V – 0.9 V = 2.4 V). In
addition, the transistor’s R
DSon
of Q1 should be low enough, when driven
by V
IN
, that the voltage drop across the transistor at maximum current
(e.g., I
CCINTmax
*R
DSon
) does not cause V
CCINT
to fall below its -5%
tolerance.
o The source of Q1 needs at least 10 uF of total capacitance in order for the
soft-start circuit to work properly. The additional bulk bypass capacitance
(not shown in the schematic) required for the V
CCINT
rail of the FPGA will
most likely meet this requirement.
-
- Input Voltage Monitoring Circuit:
o The TLC770x SVS circuit is sensitive to the rise time and source
impedance of the input power supply. If the input power supply rises
slowly and has a high source impedance, the RESET and /RESET outputs
may briefly toggle between high and low due to the point of load
converter being enabled and pulling the input power supply down slightly,
until the input voltage rises above the SVS’s trip point. Therefore, the 1.0
uF capacitor, C7, should be placed as close as possible between VDD and
GND. To further reduce the risk of this happening, a 10k ohm resistor
(R5) from the VDD pin to the SNS pin and a 0.1 uF capacitor (C8 on R7
pad)) from the SNS pin to GND were added. The RC delay created by
this capacitor and resistor prevents the SVS from tripping until the input
supply is well above the internal trip point
-
- Modifications:
o CT of TLC7733 is not connected, but can be used with a capacitor to add a
delay between the 5V rail coming up and RST = /EN1=/EN2 of TPS70402.
o Select the appropriate TLC77xx option to monitor the input supply voltage.
o For a low-cost, discrete Supply Voltage Supervisory Circuit alternative to
U1, please see reference design PR286 (Active-High Reset Output) or
PR281 (Active-Low Reset Output).