Datasheet

the transistor at maximum current (e.g., I
CCINTmax
*R
DSon
) does not cause
V
CCO
to fall below its -5% tolerance.
o The drain of Q4 needs at least 10 uF of total capacitance in order for the
soft-start circuit to work properly. The additional bulk bypass capacitance
(not shown in the schematic) required for the V
CCO
rail of the FPGA will
most likely meet this requirement.
-
- Layout: The 1.0 uF capacitor, C7, should be placed as close as possible between
VDD and GND of the TLC77xx SVS IC.
-
- Modifications:
o CT of TLC7705 is not connected, but can be used with a capacitor to add a
delay between the 5 V rail coming up and RST = /EN of TPS64203.
o Adapt for 3.3V supply by:
§ Omitting U4 circuit,
§ Replacing TLC7705 with TLC7733.
o For a low-cost, discrete Supply Voltage Supervisory Circuit alternative to
U1, please see reference design PR286 (Active-High Reset Output) or
PR281 (Active-Low Reset Output).
-
- 3.3V Configuration
o The Spartan-3 FPGA configuration and JTAG ports commonly use signals
with a 2.5-V swing. Alternatively, it is possible to use 3.3-V signals
simply by adding a few external resistors. The 3.3-V signals can cause a
reverse current that flows from certain configurations and JTAG input pins,
through the FPGA, to the V
CCAUX
power rail. Therefore, please refer to
application note SLVA159 http://focus.ti.com/lit/an/slva159a/slva159a.pdf
for implementation guidance.
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-
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