Datasheet

-
- Link to datasheets at http://focus.ti.com/lit/ds/symlink/tps64203.pdf,
http://focus.ti.com/lit/ds/symlink/tps78601.pdf,
http://focus.ti.com/lit/ds/symlink/tps79401.pdf, and
http://focus.ti.com/lit/ds/symlink/tlc7705.pdf.
-
- Link to application note SLVA156 http://focus.ti.com/lit/an/slva156/slva156.pdf
for more details on the soft-start circuit.
-
- Link to application note SLVA118 http://focus.ti.com/lit/an/slva118/slva118.pdf
to explore the thermal considerations when using linear regulators.
-
- Link to application note SLVA160 http://focus.ti.com/lit/an/slva160/slva160.pdf
for guidance on selecting a different option from the TPS642xx family.
-
- Link to application note SLVA159
http://focus.ti.com/lit/an/slva159a/slva159a.pdf when using 3.3-V JTAG ports.
IMPLEMENTATION NOTES:
-
- Sequencing: Although Xilinx FPGAs do NOT require it, this reference design
employs sequencing. This practice is consistent with good power supply design
and prevents the input power supply from being pulled down due to supporting
in-rush currents for charging large capacitive loads all at once.
-
- V
CCO
minimum ramp time: Met by Q4 soft-start circuit
-
- Power Dissipation/Thermal Issues:
o Diode D1 in SMA package can only support 3A for ambient temperatures
below 35 C. This diode will need to be increased to an SMC package or
DDPAK package in order to provide the power dissipation necessary for
higher ambient temperature. Refer to the diode’s datasheet for thermal
specifications.
o Refer to the application section of the linear regulator datasheet for
maximum power dissipation at different ambient conditions as well as
guidance on sizing the ground plane area underneath the package for
heatsinking.
-
- Designing with the TPS64203:
o The TPS64203 controller has limited current to drive the gate of the
PMOS transistor, Q3. To ensure proper operation of the controller, a
PMOS transistor with a maximum total gate charge, Q
g
, of less than 50 nC
is required.
o Omitting current sense resistor R4 and connecting ISNS to the drain of Q3,
thereby using the R
DSon
of Q3 as the current sense, results in an effective,
but slightly less accurate, current limit function.
-
- Soft Start Circuitry:
o PMOS transistor Q4 should be selected so that its threshold voltage, V
TH
,
is at least 0.9 V below the V
CCO
voltage or lower (e.g., V
TH
< 3.3 V – 0.9
V = 2.4 V). In addition, the transistor’s R
DSon
should be low enough when
driven by the output of the linear regulator so that the voltage drop across