Data Sheet
WL1801MOD,
WL1805MO
D
,
WL1831MO
D
,
WL1835MOD
SWRS152M – JULY 2013 – REVISED OCTOBER 2017
www.ti.com
Specifications
9
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WL1835MOD
5 Specifications
All specifications are measured at the module pins using the TI WL1835MODCOM8 evaluation board. All
measurements are performed with V
BAT
= 3.7 V, V
IO
= 1.8 V, 25°C for typical values with matched RF
antennas, unless otherwise indicated.
NOTE
For level-shifting I/Os with the TI WL18x5MOD, see the Level Shifting WL18xx
I/Os
Application Report.
5.1 Absolute Maximum
Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX
UNIT
V
BAT
4.8
(2)
V
V
IO
–0.5 2.1
V
Input voltage to analog pins –0.5 2.1
V
Input voltage limits (CLK_IN) –0.5 VDD_IO
V
Input voltage to all other pins –0.5 (VDD_IO + 0.5 V)
V
Operating ambient temperature –20 70
(3)
°
C
Storage temperature, T
stg
–40 85
°
C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Operating Conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) 4.8 V cumulative to 2.33 years, including charging dips and peaks
(3) In the WL18xx system, a control mechanism exists to ensure T
j
< 125°C. When T
j
approaches this threshold, the control mechanism
manages the transmitter patterns.
5.2 ESD Ratings
VALUE UNIT
V
(ESD)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001
(1)
±1000
V
Charged device model (CDM), per JEDEC specification
JESD22-C101
(2)
±
250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN TYP MAX
UNIT
V
BAT
(1)
DC supply range for all modes
2.9 3.7 4.8
V
V
IO
1.8-V I/O ring power supply voltage
1.62 1.8 1.95
V
V
IH
I/O high-level input voltage
0.65 × VDD_IO VDD_IO
V
V
IL
I/O low-level input voltage
0 0.35 × VDD_IO
V
V
IH_EN
Enable inputs high-level input voltage
1.365 VDD_IO
V
V
IL_EN
Enable inputs low-level input voltage
0 0.4
V
V
OH
High-level output voltage @ 4 mA VDD_IO –0.45 VDD_IO
V
V
OL
Low-level output voltage @ 4 mA 0 0.45
V
T
r
,T
f
Input transitions time T
r
,T
f
from 10% to
90% (digital
I/O)
(2)
1 10
ns
T
r
Output rise time from 10% to 90%
(digital pins)
(2)
C
L
< 25 pF
5.3
ns
T
f
Output fall time from 10% to 90%
(digital pins)
(2)
C
L
< 25 pF
4.9
ns
(1) 4.8 V is applicable only for 2.33 years (30% of the time). Otherwise, maximum V
BAT
must not exceed 4.3 V.
(2) Applies to all digital lines except PCM and slow clock lines