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WL1801MOD,
WL1805MO
D
,
WL1831MO
,
WL1835MOD
SWRS152M – JULY 2013 – REVISED OCTOBER 2017
www.ti.com
6
Terminal Configuration and Functions
Copyright © 2013–2017, Texas Instruments Incorporated
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Product Folder Links: WL1801MOD WL1805MOD WL1831MOD
WL1835MOD
4.1 Pin Attributes
Table 4-1 describes the module pins.
Table 4-1. Pin
Attributes
PIN NAME
PIN
NO.
TYPE/
DIR
SHUTDOWN
STATE
AFTER
POWER
UP
(1)
VOLTAGE
LEVEL
CONNECTIVITY
(2)
DESCRIPTION
(3)
1801 1805
1831 1835
Clocks and Reset Signals
WL_SDIO_CLK
8
I
Hi-Z
Hi-Z
1.8 V
v
v
v
v
WLAN SDIO clock.
Must be driven by the
host.
EXT_32K
36
ANA
–
v
v
v
v
Input sleep clock:
32.768 kHz
WLAN_EN
40
I
PD
PD
1.8 V
v
v
v
v
Mode setting: high =
enable
BT_EN
41
I
PD
PD
1.8 V
x
x
v
v
Mode setting: high =
enable
Power-Management Signals
VIO_IN
38
POW
PD
PD
1.8 V
v
v
v
v
Connect to 1.8-V
external VIO
VBAT_IN
46
POW
VBAT
v
v
v
v
Power supply input,
2.9 to 4.8 V
VBAT_IN
47
POW
VBAT
v
v
v
v
Power supply input,
2.9 to 4.8 V
TI Reserved
GPIO11
2
I/O
PD
PD
1.8 V
v
v
v
v
Reserved for future
use. NC if not used.
GPIO9
3
I/O
PD
PD
1.8 V
v
v
v
v
Reserved for future
use. NC if not used.
GPIO10
4
I/O
PU
PU
1.8 V
v
v
v
v
Reserved for future
use. NC if not used.
GPIO12
5
I/O
PU
PU
1.8 V
v
v
v
v
Reserved for future
use. NC if not used.
RESERVED1
21
I
PD
PD
1.8 V
x
x
x
x
Reserved for future
use. NC if not used.
RESERVED2
22
I
PD
PD
1.8 V
x
x
x
x
Reserved for future
use. NC if not used.
GPIO4
25
I/O
PD
PD
1.8 V
v
v
v
v
Reserved for future
use. NC if not used.
RESERVED3
62
O
PD
PD
1.8 V
x
x
x
x
Reserved for future
use. NC if not used.
WLAN Functional Block: Int Signals
WL_SDIO_CMD_1V8
6
I/O
Hi-Z
Hi-Z
1.8 V
v
v
v
v
WLAN SDIO
command
WL_SDIO_D0_1V8
10
I/O
Hi-Z
Hi-Z
1.8 V
v
v
v
v
WLAN SDIO data bit
0
WL_SDIO_D1_1V8
11
I/O
Hi-Z
Hi-Z
1.8 V
v
v
v
v
WLAN SDIO data bit
1
WL_SDIO_D2_1V8
12
I/O
Hi-Z
Hi-Z
1.8 V
v
v
v
v
WLAN SDIO data bit
2
(1) PU = pullup; PD = pulldown
(2) v = connect; x = no connect
(3) Host must provide PU using a 10-K resistor for all non-CLK SDIO signals.